riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel (by ucb-bar)
dromajo
RISC-V RV64GC emulator designed for RTL co-simulation (by chipsalliance)
riscv-mini | dromajo | |
---|---|---|
1 | 1 | |
493 | 198 | |
1.6% | 0.5% | |
3.8 | 6.0 | |
about 2 months ago | about 2 months ago | |
Scala | C++ | |
GNU General Public License v3.0 or later | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-mini
Posts with mentions or reviews of riscv-mini.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-15.
dromajo
Posts with mentions or reviews of dromajo.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-06-15.
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Tips on building a RISC-V processor on FPGA
Always test each of your changes on a battery of tests, like the riscv-tests. Have a way to generate a commit log of instructions and write back values and compare against an ISA simulator like spike or https://github.com/chipsalliance/dromajo.
What are some alternatives?
When comparing riscv-mini and dromajo you can also consider the following projects:
riscv-boom - SonicBOOM: The Berkeley Out-of-Order Machine
riscv-tests
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
chisel - Chisel: A Modern Hardware Design Language
RISCV-FiveStage - Marginally better than redstone
rocket-chip - Rocket Chip Generator