riscv-gcc
By riscvarchive
riscv-opcodes
RISC-V Opcodes (by riscv)
| riscv-gcc | riscv-opcodes | |
|---|---|---|
| 3 | 5 | |
| 359 | 615 | |
| - | 1.1% | |
| 0.0 | 7.7 | |
| 12 months ago | 3 days ago | |
| Python | ||
| GNU General Public License v3.0 only | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
riscv-gcc
Posts with mentions or reviews of riscv-gcc.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-09-15.
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How to extend Risc-V P extension in riscv-gcc and riscv-binutils?
gcc: https://github.com/riscv-collab/riscv-gcc/pull/258
-
riscv64-unknown-elf-objdump
It does not appear to have been packaged in fedora from what I can tell. You could try to build it from source. https://github.com/riscv-collab/riscv-gcc
- Sipeed tease new Allwinner D1 board
riscv-opcodes
Posts with mentions or reviews of riscv-opcodes.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-04-28.
-
How to improve the RISC-V specification
It uses machine-readable specs from https://github.com/riscv/riscv-opcodes ; yet I needed to extract immediate bit scrambling from their LaTeX sources :). I wonder if there is an easier way. Anyways, the opcode semantics are hand-coded and it simulates enough to boot linux.
- Help needed in building cavatools
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RISC-V remaining insn free space
A couple of hours work would allow someone to work it out exactly by parsing the files in https://github.com/riscv/riscv-opcodes. I don't know whether the existing parse.py explicitly works this out. It does check for conflicts. If it doesn't provide this information now then it should be easy to add.
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How to extend Risc-V P extension in riscv-gcc and riscv-binutils?
Add instruction's match and mask values and optionally add DECLARE_INSN definitions (include/opcode/riscv-opc.h). You can use riscv-opcodes to generate those mask/match values.
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Programming 101: writing a RISCV assembler - the worlds smallest!
I'm a bit surprised René doesn't know about either https://github.com/riscv/riscv-opcodes or https://github.com/michaeljclark/riscv-meta
What are some alternatives?
When comparing riscv-gcc and riscv-opcodes you can also consider the following projects:
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
riscv-meta - RISC-V Instruction Set Metadata
rvv-llvm - This repository is outdated, support for RISC-V is now developed in upstream LLVM
riscv-isa-sim - Spike, a RISC-V ISA Simulator
riscv-binutils-gdb - RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
binutils-gdb
riscv-binutils-devmemo - binutils development memo (for RISC-V)
cavatools - Cavatools is a RISC-V architectural simulator.
riscv-isa-manual - RISC-V Instruction Set Manual
riscv-gcc vs riscv-gnu-toolchain
riscv-opcodes vs riscv-meta
riscv-gcc vs rvv-llvm
riscv-opcodes vs riscv-isa-sim
riscv-gcc vs riscv-binutils-gdb
riscv-opcodes vs binutils-gdb
riscv-gcc vs binutils-gdb
riscv-opcodes vs riscv-binutils-gdb
riscv-gcc vs riscv-binutils-devmemo
riscv-opcodes vs cavatools
riscv-opcodes vs riscv-binutils-devmemo
riscv-opcodes vs riscv-isa-manual