prjtrellis
prince
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prjtrellis | prince | |
---|---|---|
5 | 1 | |
381 | 7 | |
0.0% | - | |
8.5 | 3.5 | |
3 months ago | 4 months ago | |
Python | Verilog | |
GNU General Public License v3.0 or later | BSD 2-clause "Simplified" License |
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prjtrellis
- Project Trellis – Documenting the Lattice ECP5 FPGA Bitstream Format
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Learning Verilog and FPGA
Yosys, the underlying compiler of ice studio, also targets the much bigger ECP5 FPGA, also by Lattice, which is called Project Trellis: https://github.com/YosysHQ/prjtrellis
Yosys functions more like a software open source tool. So command line compiling. It also has a REPL. It is very quick compared to the commercial solutions. Especially around compile times which can take seconds instead of minutes. YMMV, but I think the consensus is that it's a lot more convenient to use.
In general the hardware toolchains feel very ancient compared to software toolchains.
- Project Trellis – fully open-source flow for ECP5 FPGAs, using Yosys and nextpnr
- 5% of 666 Python repos had comma typo bugs (inc V8, TensorFlow and PyTorch)
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Lattice ECP3 - any way of working withe them with free license ?
Not that it will lead to anything soon, you could put a feature request in at Project Trellis and offer to test things, or provide hardware if you have extra.
prince
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Learning Verilog and FPGA
I would also recommend to use non-blocking assignments only for register updates, not in any description of combinational logic. It is (IMHO) much easier to read Verilog code with blocking assignments for logic since you basically can read the statements one after the other and mentally think that the RHS on a statement has been updated.
IF I may point to my own code, the prince cipher core shows how I use non-blocking assignments in a very simple reg update process. The datapath is in a separate, pure combinational process. And the control path is handled by the finite state machine update logic process at the end.
https://github.com/secworks/prince/blob/master/src/rtl/princ...
The SystemVerilog always_comb and always_ff type of processes makes the distincion much clearer. But the same strategy holds for Verilog, and IMHO helps out understand the code. And often makes it less complex.
What are some alternatives?
Vulkan-ValidationLayers - Vulkan Validation Layers (VVL)
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
apio - :seedling: Open source ecosystem for open FPGA boards
quickstep - Quickstep project
6502-exp - 6502 Computer FPGA Peripherals
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
vhdl-tutorial
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)