prjtrellis
icestorm
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| prjtrellis | icestorm | |
|---|---|---|
| 5 | 7 | |
| 381 | 945 | |
| 0.0% | 1.9% | |
| 8.5 | 0.0 | |
| 3 months ago | 7 days ago | |
| Python | Python | |
| GNU General Public License v3.0 or later | ISC License |
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prjtrellis
- Project Trellis – Documenting the Lattice ECP5 FPGA Bitstream Format
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Learning Verilog and FPGA
Yosys, the underlying compiler of ice studio, also targets the much bigger ECP5 FPGA, also by Lattice, which is called Project Trellis: https://github.com/YosysHQ/prjtrellis
Yosys functions more like a software open source tool. So command line compiling. It also has a REPL. It is very quick compared to the commercial solutions. Especially around compile times which can take seconds instead of minutes. YMMV, but I think the consensus is that it's a lot more convenient to use.
In general the hardware toolchains feel very ancient compared to software toolchains.
- Project Trellis – fully open-source flow for ECP5 FPGAs, using Yosys and nextpnr
- 5% of 666 Python repos had comma typo bugs (inc V8, TensorFlow and PyTorch)
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Lattice ECP3 - any way of working withe them with free license ?
Not that it will lead to anything soon, you could put a feature request in at Project Trellis and offer to test things, or provide hardware if you have extra.
icestorm
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Framework Laptop feature requests – RISC-V Mainboard
I'd also vote for an FPGA Mainboard, ideally Lattice, ideally iCE40, and ideally compatible with Project IceStorm (Yosys, Arachne-pnr, and IceStorm) open source tools:
https://github.com/YosysHQ/icestorm
Think something similar to MiSTer FPGA -- but in a laptop form factor, and able to run all sorts of "soft" CPUs, i.e.:
https://opencores.org/projects?expanded=Processor
- Are there any resources detailing how synthesis happens for a particular FPGA?
- Building the SAP-2 on an FPGA
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Learning Verilog and FPGA
As others have already mentioned the Lattice ice40 family is supported by OSS chains through project icestorm [0].
There were some nice boards floating around though you may have to watch out for supply chain issues still plaguing this market. Examples:
- icoboard: has the 8k LUTs chip, comes with soldered PMODs[1], if you get it watch out as you either need a RaspberryPI with GPIOs soldered to program it, or you purchase their USB FTDI interface in addition. See: http://icoboard.org/
- iCEBreaker, comes with the 5k LUTs chip, has the USB-FTDI interface built-in, but you need to solder the PMODs yourself. See: https://www.crowdsupply.com/1bitsquared/icebreaker-fpga#prod...
[0] https://github.com/YosysHQ/icestorm
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Thoughts on OSFPGA?
You know the best part about Lattice FPGAs? The iCE40 bitstream has been reverse-engineered. As a result, you can delete Diamond and use a completely open-source toolchain instead. It's so much cleaner, easier, and less bloated that it just shows how awful all the vendor tools have gotten.
- Project IceStorm: open-source toolchain for Lattice iCE40 FPGAs
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J2 open processor: an open source processor using the SuperH ISA
>The rest of this page explains how to compile and install a "bitstream" file to implement this processor in a cheap (about $50) FPGA board, then how to build Linux for that board and boot it to a shell prompt.
>Numato: The cheapest usable FPGA development board ($50 US) the j2 build system currently targets is the Numato Mimas v2 (also available on amazon). It contains a Xlinux "Spartan 6" LX9 FPGA that can run a J2 at 50mhz, 64 megs of SDRAM, USB2 mini-B, and a micro-sd card slot.
Nice!
But, it would be an additional serious "would be nice" -- if this could run on Lattice FPGA's / IceStorm Open Source Toolchain:
https://www.latticesemi.com/Products
http://www.clifford.at/icestorm/
https://github.com/YosysHQ/icestorm
What are some alternatives?
Vulkan-ValidationLayers - Vulkan Validation Layers (VVL)
ghdl-yosys-plugin - VHDL synthesis (based on ghdl)
quickstep - Quickstep project
apio - :seedling: Open source ecosystem for open FPGA boards
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
prince - The Prince lightweight block cipher in Verilog.
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
dbus_ti_link_uart_verilog - Verilog dbus (TI transfer bus) implementation and bridge to UART. High-performance link with TI calculators such as TI-89.
abc - ABC: System for Sequential Logic Synthesis and Formal Verification
6502-exp - 6502 Computer FPGA Peripherals
vhdl-tutorial