panologic
PanoLogic Zero Client G1 reverse engineering info (by tomverbeure)
pin-uart
FPGA board-level debugging and reverse-engineering tool (by alexforencich)
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The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
panologic
Posts with mentions or reviews of panologic.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-12.
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Reverse engineering unsocumented FPGA board?
I have reverse engineered many FPGA boards.
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Cheap (or Free FPGAs)
Here is my GitHub repo: https://github.com/tomverbeure/panologic
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Risc-v with minimum number of gates
That's the approach I use in all my hobby projects. Do I really need that I2C controller? Of course not, I just bitbang it on a VexRiscv CPU...
pin-uart
Posts with mentions or reviews of pin-uart.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-03-12.
- Pin UART FPGA board-level debugging and reverse-engineering tool
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Reverse engineering unsocumented FPGA board?
This concept can be handy, https://github.com/alexforencich/pin-uart
What are some alternatives?
When comparing panologic and pin-uart you can also consider the following projects:
serv - SERV - The SErial RISC-V CPU
clash-spaceinvaders - Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
vivado-risc-v - Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro
red-pitaya-notes - Notes on the Red Pitaya Open Source Instrument
make_for_vivado - experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
color3 - Information about eeColor Color3 HDMI FPGA board
panologic-g2 - Pano Logic G2 Reverse Engineering Project