nasm
riscv-asm-manual
| nasm | riscv-asm-manual | |
|---|---|---|
| 6 | 8 | |
| 2,152 | 1,356 | |
| 2.0% | 0.9% | |
| 3.2 | 3.7 | |
| 4 days ago | 1 day ago | |
| Assembly | ||
| GNU General Public License v3.0 or later | Creative Commons Attribution 4.0 |
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nasm
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RISC-V Assembler: Arithmetic
> fringe ISAs
Itanium fringe? You’re clueless and have no credibility.
> Assembly is meant to map directly to the way the machine code is written
This is just false.
https://github.com/netwide-assembler/nasm/blob/master/asm/as...
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How to improve at x86/C?
Try https://nasm.us/ as a modern way to use assembly.
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Help needed for asm related project
Assembly is machine specific, have a look at NASM for a more generic assembly language. https://nasm.us/
- Nasm - A cross-platform x86 assembler with an intel-like syntax
- Nasm – A cross-platform x86 assembler with an Intel-like syntax
- NASM Assembly Language Tutorials
riscv-asm-manual
- RISC-V Assembler: Arithmetic
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RISC-V assembler input file format
This document has most of the explanations about the input format: https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md. There are some small missing bits but all the directives like .text are there.
- If you were to start your coding journey from zero, what would be your plan?
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Question about RISC-V development
The is a C and C++ toolchain available https://github.com/riscv-collab/riscv-gnu-toolchain If you feeling brave, https://github.com/riscv-non-isa/riscv-asm-manual/blob/master/riscv-asm.md
- Is there any documentation relates to the riscv-gnu-toolchain ?
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Examples of RISC-V Assembly Programs
> Note: "jalr zero, 1b" can also be written as "j 1b", "jalr zero, 0(ra)" can be written as "ret"
`j` and `ret` are so-called "pseudo instructions" [1], not compressed instructions.
Pseudo instructions are just shortcuts used in assembly language to pretend that some common operations really "exist" with the need to type (or display) the real, more complex instructions. `nop` is a common pseudo instruction. RISC-V has `nop` instructions, but, instead, the "do nothing instruction" is canonically encoded as `addi x0, x0, 0`.
The compressed instruction set (a.k.a "extension C") is a subset of the full [2] instruction set, in which a restricted combinations of operands are possible. The assembly (human readable) code of the compressed instruction set looks similar to that of the full instruction set (including pseudo instructions), but they are encoded as completely different binary sequences.
[1] https://github.com/riscv/riscv-asm-manual/blob/master/riscv-...
[2] https://riscv.org/wp-content/uploads/2019/06/riscv-spec.pdf#...
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RISCV Assembly and absolute addressing ?
This should be helpful https://github.com/riscv/riscv-asm-manual/blob/master/riscv-asm.md
- Absolute beginner to RISC-V, where do I start?
What are some alternatives?
yasm - Yasm Assembler mainline development tree
riscv-elf-psabi-doc - A RISC-V ELF psABI Document
compiler-explorer - Run compilers interactively from your web browser and interact with the assembly
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
Chronos - A low level language that closely resembles assembly.
glibc - GNU Libc
riscv-isa-manual - RISC-V Instruction Set Manual
riscv-gnu-toolchain - GNU toolchain for RISC-V, including GCC
arduino-6502ctl - Arduino 6502 Controller
computer-science - :mortar_board: Path to a free self-taught education in Computer Science!
curriculum - The open curriculum for learning web development
riscv-c-api-doc - Documentation of the RISC-V C API