learn-fpga VS riscv-v-spec

I've followed this tutorial recently, and it's amazing:

https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/...

The author includes detailed instruction for how to build a micro-controller in Verilog on an icestick, starting from a very simple blinker all the way to a functional RISC-V core.

My other suggestion would be: for most of the toolchain, skip your package manager and directly install the binary artifacts published on this Github repo:

https://github.com/YosysHQ/oss-cad-suite-build

You'll spare yourself a world of pain.

You might want to look at https://github.com/BrunoLevy/learn-fpga

Lattice Icestick is pretty cheap and has just enough LUTs to run a small riscv. Also check out https://github.com/BrunoLevy/learn-fpga

Thanks Bruno Levy

These are good starting points: https://github.com/BrunoLevy/learn-fpga/ and, from there, https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/README.md.

The best point-of-entry for "tiny" MCUs these days is FemtoRV32-Quark or SERV. I also maintain my own small RISC-V core (Minimax), though it's early on in graduating from "experiment" to "real design".

Rust blinky on RISC-V soft core If you were looking for, an introduction example of an embedded Rust program, running on a RISC-V soft core, check out this blinky that is using the FemtoRV .

Nope - that's all there is.

It's possible to be incredibly expressive in Verilog and VHDL. This implementation is written in VHDL, which has an outdated reputation for being long-winded.

Also worth a look: FemtoRV32 Quark [0], which is written in Verilog.

[0]: https://github.com/BrunoLevy/learn-fpga/blob/master/FemtoRV/...

Here are some resources I can recommend:

RVV spec (also look at the examples in the repo): https://github.com/riscv/riscv-v-spec/blob/master/v-spec.ado...

RVV intrinsics viewer: https://dzaima.github.io/intrinsics-viewer

Tutorial: RISC-V Vector Extension Demystified (3 hour video going over every instruction): https://youtu.be/oTaOd8qr53U

RISC-V Vector extension in a nutshell: https://fprox.substack.com/p/risc-v-vector-extension-in-a-nu...

If you want to see a more complex example/real world application, then you might also be ibterested ib my article about vectorizing unicode conversions: https://camel-cdr.github.io/rvv-bench-results/articles/vecto...

In terms of development I'd recommend using qemu and a cross compiler, or if you want hardware try to get the kendryte k230 (currently the only sbc with rvv 1.0 support) or wait a bit for better hardware (BPI-F3 and sg2380 should release this year).

And this isn't just some theoretical or something unlikely to happen - the official spec already contains such a bug. If the writers of the spec can't get things right, even with the small amount of code in the spec, I don't have high hopes that less informed programmers will. RVV being absurdly complicated (IMO, compared to SVE2 and AVX10) doesn't help its cause here.

Will the reference one actually be the most optimal one on future hardware?

I'll do a deep dive into the https://gms.tf/riscv-vector.html#getting-started tutorial, and probably pop the proverbial stack and just study RVV 0.7.1 on its own (using https://github.com/riscv/riscv-v-spec/releases/tag/0.7.1).

I see your point. You can file a request for it at https://github.com/riscv/riscv-v-spec/issues if you want to pitch it to the relevant ISA bodies. The bar for implementing it pretty high.

It's not "unusual"; using data registers for mask is a valid tradeoff especially for low-end implementations, whereas higher-end architectures can easily use shadow registers. Discussed in depth at https://github.com/riscv/riscv-v-spec/issues/811