internal_logic_analyzer VS DDR

Compare internal_logic_analyzer vs DDR and see what are their differences.

internal_logic_analyzer

An internal logic analyzer/scope for FPGA's (by buttercutter)
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DDR

A simple DDR3 memory controller (by buttercutter)
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internal_logic_analyzer DDR
1 8
1 40
- -
0.0 0.0
over 6 years ago over 1 year ago
C++ Verilog
GNU General Public License v3.0 only GNU General Public License v3.0 only
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internal_logic_analyzer

Posts with mentions or reviews of internal_logic_analyzer. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-05-04.
  • FPGA internal logic analyzer
    6 projects | /r/FPGA | 4 May 2021
    I have written my own ILA module at https://github.com/promach/internal_logic_analyzer . However, I am not sure how to code the verilog module that transmits the data to host cpu as well as the cpu software that actually processes the internally captured FPGA signals/data and display them accordingly ?

DDR

Posts with mentions or reviews of DDR. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2021-05-04.