hdl_rosetta_stone
writing up a few examples using different languages and tools, mostly for personal learning. (by TripRichert)
xpm_vhdl
A translation of the Xilinx XPM library to VHDL for simulation purposes (by fransschreuder)
| hdl_rosetta_stone | xpm_vhdl | |
|---|---|---|
| 4 | 2 | |
| 4 | 45 | |
| - | - | |
| 5.7 | 3.6 | |
| 5 days ago | about 2 months ago | |
| Verilog | VHDL | |
| MIT License | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hdl_rosetta_stone
Posts with mentions or reviews of hdl_rosetta_stone.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-04-25.
- Inferred BRAM based FIFO with mismatched input and output data widths
-
Vector-packing algorithm
I would write a module that held back the last element in a stream until 8 slots were passed, then let it pass through with a tlast signal. Something like this https://github.com/TripRichert/hdl_rosetta_stone/blob/main/verilog/hdl/axistream_add_tlast.v command the tlast every 8 elements, and don't raise tvalid on your inactive element inputs.
-
Gearbox FIFO implementation
https://github.com/TripRichert/hdl_rosetta_stone/blob/main/verilog/hdl/axistream_unpack.v https://github.com/TripRichert/hdl_rosetta_stone/blob/main/verilog/hdl/axistream_unpack.v (where unpack's bitwidth is 2 and NUM_PACK is 32, and pack's bitwidth is 2 and NUM_PACK is 33).
- Data flow into a top module
xpm_vhdl
Posts with mentions or reviews of xpm_vhdl.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-04-25.
What are some alternatives?
When comparing hdl_rosetta_stone and xpm_vhdl you can also consider the following projects:
Experiments - Assorted experiments and proof-of-concept code