hdcp | litedram | |
---|---|---|
3 | 6 | |
35 | 359 | |
- | - | |
0.0 | 6.4 | |
over 1 year ago | about 1 month ago | |
C++ | Python | |
GNU General Public License v3.0 or later | GNU General Public License v3.0 or later |
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Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
hdcp
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Displayport: A Better Video Interface
https://github.com/intel/hdcp
Grab it now before Intel deletes it completely.
HDCP is really a very ugly protocol designed just for anti-copying, I wouldn't build anything relying on it, and everything is harder with HDCP from an AV integration perspective. If you have long links that you want to secure, use something like SDVoE with encryption and authentication (bits are easily flipped in HDCP).
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How can I watch amazon primevideo at 1080p on linux?
Intel actually provides software to allow HDCP functionality on Linux. https://github.com/intel/hdcp
- How many more years until we have a completely open source RISC-V SOC?
litedram
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How Much Would It Cost For A Truly Open Source RISC-V SOC?
I could be wrong, but I don't think the LiteX DRAM PHY is using the UG586 block. Here's the Litex Series 7 DRAM PHY source code - it appears to be hardcoding the PHY logic. The Lattice ECP5 code in that directory does the same thing.
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I am trying to avoid AXI Bus for DDR3 access on Arty A7
Try https://github.com/enjoy-digital/litedram with a RAW or FIFO interface. It is in Migen, a python DSL HDL, but you could just use the output.
- LiteDRAM – A fully open-source memory controller targeting LPDDR4/5 for FPGA
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Suggest advance project ideas
You could try to implement a PCIe root complex for FOSS SoCs, connecting to e.g. Wishbone as the main bus. There's already some DDR3 controller (or this one) and USB Host controller out there, and even device-side PCIe, but no FOSS host-side PCIe that I know of. Probably quite a difficult job though, even sticking to the lower-speed PCIe 1.
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How many more years until we have a completely open source RISC-V SOC?
So for instance (and AFAI understand...) the DDR2 sdram controller uses a generic PHY (https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/gensdrphy.py) , but the DDR3 one has to talk to some vendor-specific PHY (e.g. https://github.com/enjoy-digital/litedram/blob/master/litedram/phy/s7ddrphy.py ). The controller itself is vendor-agnostic (https://github.com/enjoy-digital/litedram/blob/master/litedram/core/controller.py). On Xilinx FPGA it doesn't rely on MIG at all.
What are some alternatives?
SaxonSoc - SoC based on VexRiscv and ICE40 UP5K
litex - Build your hardware, easily!
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
SpinalHDL - Scala based HDL
litepcie - Small footprint and configurable PCIe core
kvm-switch - Control hardware KVM/Matrix devices when your mouse moves to the edge of the screen
OSCAR
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
OpenSERDES - Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.