gateware
IP submodules, formatted for easier CI integration (by betrusted-io)
verilog-wishbone
Verilog wishbone components (by alexforencich)
gateware | verilog-wishbone | |
---|---|---|
1 | 1 | |
26 | 99 | |
- | - | |
5.7 | 0.0 | |
5 months ago | 4 months ago | |
Verilog | Python | |
GNU General Public License v3.0 or later | MIT License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
gateware
Posts with mentions or reviews of gateware.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
-
Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
verilog-wishbone
Posts with mentions or reviews of verilog-wishbone.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
-
Share some github FPGA projects (bonus if they include C++, Python, or other files)
A lot of reuse from other FOSH projects, including Litex, SpinalHDL, betrusted & u/alexforencich verilog-wishbone. Thanks to all of them :-)
What are some alternatives?
When comparing gateware and verilog-wishbone you can also consider the following projects:
verilog-ethernet - Verilog Ethernet components for FPGA implementation
litex - Build your hardware, easily!
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
SpinalHDL - Scala based HDL
WARP_Core - Wilson AXI RISCV Processor Core
BYU_PYNQ_PR_Video_Pipeline - The Demo that was presented at FCCM.
corundum - Open source FPGA-based NIC and platform for in-network compute
gateware vs verilog-ethernet
verilog-wishbone vs litex
gateware vs litex
verilog-wishbone vs verilog-ethernet
gateware vs satcat5
verilog-wishbone vs soft_riscv
gateware vs SBusFPGA
verilog-wishbone vs SpinalHDL
gateware vs WARP_Core
verilog-wishbone vs BYU_PYNQ_PR_Video_Pipeline
verilog-wishbone vs corundum
verilog-wishbone vs SBusFPGA