fusesoc-cores
FuseSoC standard core library (by fusesoc)
tiny-cores
Collection of assorted small cores (by fusesoc)
| fusesoc-cores | tiny-cores | |
|---|---|---|
| 1 | 1 | |
| 97 | 9 | |
| - | - | |
| 4.5 | 10.0 | |
| 6 months ago | over 3 years ago | |
| Verilog | ||
| - | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fusesoc-cores
Posts with mentions or reviews of fusesoc-cores.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-18.
tiny-cores
Posts with mentions or reviews of tiny-cores.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-11-18.
What are some alternatives?
When comparing fusesoc-cores and tiny-cores you can also consider the following projects:
opentitan - OpenTitan: Open source silicon root of trust
surf - A huge VHDL library for FPGA development
fusesoc - Package manager and build abstraction tool for FPGA/ASIC development
axi - AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication
chisel - Chisel: A Modern Hardware Design Language
basejump_stl - BaseJump STL: A Standard Template Library for SystemVerilog