cavatools
Cavatools is a RISC-V architectural simulator. (by phaa-eu)
riscv-opcodes
RISC-V Opcodes (by riscv)
| cavatools | riscv-opcodes | |
|---|---|---|
| 2 | 5 | |
| 4 | 627 | |
| - | 2.4% | |
| 4.0 | 8.1 | |
| 11 months ago | 11 days ago | |
| C++ | Python | |
| Apache License 2.0 | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
cavatools
Posts with mentions or reviews of cavatools.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-05-09.
-
Help needed in building cavatools
here is what i did. $git clone https://github.com/phaa-eu/cavatools then cloned all the 4 repos into a directory riscv-tools. checkedout risv-opcodes to relavant commit.
riscv-opcodes
Posts with mentions or reviews of riscv-opcodes.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-04-28.
-
How to improve the RISC-V specification
It uses machine-readable specs from https://github.com/riscv/riscv-opcodes ; yet I needed to extract immediate bit scrambling from their LaTeX sources :). I wonder if there is an easier way. Anyways, the opcode semantics are hand-coded and it simulates enough to boot linux.
- Help needed in building cavatools
-
RISC-V remaining insn free space
A couple of hours work would allow someone to work it out exactly by parsing the files in https://github.com/riscv/riscv-opcodes. I don't know whether the existing parse.py explicitly works this out. It does check for conflicts. If it doesn't provide this information now then it should be easy to add.
-
How to extend Risc-V P extension in riscv-gcc and riscv-binutils?
Add instruction's match and mask values and optionally add DECLARE_INSN definitions (include/opcode/riscv-opc.h). You can use riscv-opcodes to generate those mask/match values.
-
Programming 101: writing a RISCV assembler - the worlds smallest!
I'm a bit surprised René doesn't know about either https://github.com/riscv/riscv-opcodes or https://github.com/michaeljclark/riscv-meta
What are some alternatives?
When comparing cavatools and riscv-opcodes you can also consider the following projects:
riscv-isa-sim - Spike, a RISC-V ISA Simulator
riscv-meta - RISC-V Instruction Set Metadata
riscv-gcc
binutils-gdb
riscv-binutils-gdb - RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
riscv-binutils-devmemo - binutils development memo (for RISC-V)
riscv-isa-manual - RISC-V Instruction Set Manual