riscv-gnu-toolchain VS openc910

That shouldn't be news.

Other than the CanMV-K230 (Kendryte K230, single 1.6 GHz C908 core implementing RVV) which just started shipping in the last two weeks, every RISC-V board with RVV has either C906 or C910 cores which implement draft 0.7.1.

Those CPU cores were announced in mid 2019 (when RVV 0.7.1 was the current draft) and boards using them start arriving in mid to late 2021.

RVV 1.0 boards will start arriving in force next year, probably starting with the StarFive JH8110 SoC, and (apparently, though I'm not sure I believe it) an update of the SG2042 in the Pioneer, and also the 16 core (but faster cores) SG2380.

> Do you happen to have the name of the gcc branch

The branch has been deleted from the official repo. I have a snapshot on my github:

https://github.com/brucehoult/riscv-gnu-toolchain

Note that it is primarily binutils which understands RVV 0.7.1. GCC understands it only to the extent of accepting "v" in "-march" and passing the right flags to the assembler. This enables using the gcc driver to build .s files and inline RVV asm in C. There is no support for RVV intrinsic functions or auto-vectorisation.

It's also a somewhat old gcc. I use it to build .o files from assembly language, and then link them with C compiled by a newer gcc or llvm. Or not, most of the time gcc 9 is fine.

THead have RVV 0.7.1 support in newer gcc, but I haven't been tracking that closely.

The TH1520 has much faster memcpy speeds at every level of cache and DRAM.

https://hoult.org/JH7110_memcpy.txt

https://hoult.org/JH7110_memcpy.txt

And yet ... both Richard Jones at Fedora and I have found that the VisionFive 2 is actually slightly faster at building software packages!

My result was that building the same binutils + gcc + newlib snapshot (an old one with RVV 0.7.1 support)...

https://github.com/brucehoult/riscv-gnu-toolchain

... the VisionFive 2 takes 108 minutes while the Lichee Pi 4A takes 122 minutes.

That's with the supplied fan on the LPi4A (and confirmed it's not throttling) and no cooling at all on the VisionFive 2. I used the same Samsung external USB3 SSD on both -- the VisionFive 2 gets slightly faster transfer speeds (IIRC 190 MB/s vs 160) with that, but that's not enough to matter: just 12s difference on the time to tar up the source directory, compared to a 14 minute build time difference. Both have enough RAM to cache everything anyway.

> VF2 GPU: IMG BXE-4-32 Lichee Pi: ?? Anyone?

BXM-4-64

I've also found the 1.5 GHz in-order VF2 does remarkably well vs the 1.85 GHz OoO LPi4A on software build tasks, though not as extreme as Richard shows.

I'm lazy and using the original Image-55 on my 8 GB VF2, and the Debian that came preloaded in the eMMC on the LPi4A. My mass-production LPi4A arrived yesterday, I haven't tried it yet, tests are on the beta board that arrived a couple of months ago.

On pure CPU core + L1 cache tests (e.g. https://hoult.org/primes.txt) the LPi4A is considerably faster.

The LPi4A is also much faster on memcpy tests.

https://hoult.org/TH1520_memcpy.txt

https://hoult.org/JH7110_memcpy.txt

My build test is an RVV 0.7.1-enabled snapshot of the gnu toolchain (gcc 9.2) that I use on the TH1520 and SG2042. Newlib, non-multilib (just rv64gcv) build. I used the same Samsung 2 TB external USB3 SSD drive for src/build trees on both boards. https://github.com/brucehoult/riscv-gnu-toolchain

VF2:

real 107m52.116s

To build rvv programs I use brucehoults rvv 0.7.1 toolchain and some assembly macros, so I can write a subset of rvv 1.0 that I can run on rvv 0.7.1: https://github.com/brucehoult/riscv-gnu-toolchain https://github.com/camel-cdr/rvv-d1/blob/main/rvv-rollback.S

I'm using a rvv 0.7.1 toolchain, which doesn't support the rvv 1.0 mnemonics.

Step 1. Build the RISC-V GNU toolchain suitable for compiling and assembling RVV 0.7.1 instructions, and that would be https://github.com/brucehoult/riscv-gnu-toolchain. For grins I built this on a RISC-V machine, the Unmatched. It took a few hours, but there's something sublime about using RISC-V everywhere you can.

> I'm pretty sure that SiFive isn't allowed to sell their RISC-V core designs to any Chinese company already.

The JH7110 SoC from the Chinese firm Starfive uses SiFive's U74 core. Eswin, also Chinese uses SiFive's P550 core in their upcoming EIC7700 SoC.

> All Chinese RISC-V core designs have been proprietary designs thus far.

There is the OpenC910 [1] and OpenXiangShan [2].

[1] https://github.com/T-head-Semi/openc910

Note that the C910 CPU cores used in this chip are in fact open source:

https://github.com/T-head-Semi/openc910

(C920 is just C910 plus RVV draft 0.7.1 vector unit which pretty much no software uses anyway, sadly)

The Milk-V Pioneer uses a C910 CPU, which has been open sourced by t-head: https://github.com/T-head-Semi/openc910

More precisely, a Chinese university assembled a rack containing 48 [1] commercially available SBCs [2], each with a Chinese-designed and made SG2042 SoC with 64 C910 CPU cores. The C910 was designed in China in 2018/19 and open-sourced in October 2021, on Microsoft's github site.

https://github.com/T-head-Semi/openc910

The SG2042 is the most powerful RISC-V SoC available today.

In which direction is the technology transfer going?

[1] or possibly 24 dual-socket boards, shown at the RISC-V Summit China in August

[2] get your own here https://www.crowdsupply.com/milk-v/milk-v-pioneer

For "coming down the pipeline" they're essentially free.

Today, the c910 is an Apache 2, hardware proven out of order core on GitHub here https://github.com/T-head-Semi/openc910 a little slower than an RPi3's core.

Here is the source code* for the CPU:

https://github.com/T-head-Semi/openc910

* AFAIK they didn't opensource the pre ratification vector extension implementation they ship with the taped out chip.

The source RTL for the roughly Arm A72-equivalent cores used in this were open-sourced several years ago.

https://github.com/T-head-Semi/openc910

The same cores are used in the 64 core SG2042 workstation/server SoC.

It's a shame, because it was the best design from ARM; they're now focusing on Cortex-A7x and Cortex-X, which aren't anywhere as power efficient[0].

Meanwhile, their revised Cortex-A57 has been surpassed in performance/power/area by several RISC-V microarchitectures, such as SiFive's U74[1], used in the VisionFive2 and Star64, or even the open source XuanTie C910[2][3].

0. https://www.youtube.com/watch?v=s0ukXDnWlTY

1. https://www.sifive.com/cores/u74

2. https://xrvm.com/cpu-details?id=4056743610438262784

3. https://github.com/T-head-Semi/openc910