axi_softcores
By tambewilliam
arrowzip
A ZipCPU based demonstration of the MAX1000 FPGA board (by ZipCPU)
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| axi_softcores | arrowzip | |
|---|---|---|
| 1 | 3 | |
| 0 | 19 | |
| - | - | |
| 0.0 | 0.0 | |
| over 4 years ago | almost 3 years ago | |
| Verilog | Verilog | |
| - | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
axi_softcores
Posts with mentions or reviews of axi_softcores.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-02-01.
arrowzip
Posts with mentions or reviews of arrowzip.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-11.
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C++ Verification Testbench Best-Practice Resources?
I have built a lot of open-source C++ tooling for design verification. You can find a lot of my C++ models posted on my Github. Example C++ models include: UART, SPI/DSPI/QSPI Flash, SD-Card (SPI-based interface), VGA Video, Ethernet MDIO, PS/2 mouse, OLED display, SDRAM and more. (I've even simulated PLLs using C++ models ...) I have also written extensively about doing so at ZipCPU.com.
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AXI Quad SPI 3.2 Flash programming scripts
Here's the flash controller repo I use. There's a flash controller in there for SPI, Dual SPI, and Quad SPI. The Dual and Quad SPI controllers need a device specific startup script to get them into the right mode. This script should be fairly well explained by the comments. You should find at least one of these controllers that works for you. More recent versions of the controller have a Wishbone arbiter within them -- they're just not checked in the repo yet. (DSPI, QSPI). This makes it so the design fully supports two two Wishbone ports: a config port by which you can send any value and the memory mapped read port. (You can't use both at the same time.)
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SDR SDRAM Controller in Verilog (MT48LC16M16)
If it would help, here are two SDRAM controllers: The first is for a winbond W9825G6JH (4M x 4 banks x 16 bits). It was designed for the XuLA-LX25 FPGA board, although it also works on my MAX-1000 board from Arrow as well. Beware, the clock needs to be offset 90 degrees from the data. The second controller works on an ISSI IS42S16100H/IS45S16100H SDRAM. Both use Wishbone (pipeline) interfaces. If you aren't using Wishbone, you might need a converter to ... whatever bus protocol you are using.
What are some alternatives?
When comparing axi_softcores and arrowzip you can also consider the following projects:
dbgbus - A collection of debugging busses developed and presented at zipcpu.com
qspiflash - A set of Wishbone Controlled SPI Flash Controllers
videozip - A ZipCPU SoC for the Nexys Video board supporting video functionality
sdspi - SD-Card controller, using either SPI, SDIO, or eMMC interfaces
openarty - An Open Source configuration of the Arty platform
zbasic - A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
vgasim - A Video display simulator