X86-64-semantics
Semantics of x86-64 in K (by kframework)
riscv-formal
RISC-V Formal Verification Framework (by SymbioticEDA)
X86-64-semantics | riscv-formal | |
---|---|---|
1 | 10 | |
130 | 550 | |
1.5% | 3.6% | |
10.0 | 0.0 | |
about 4 years ago | about 2 years ago | |
Assembly | Verilog | |
GNU General Public License v3.0 or later | ISC License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
X86-64-semantics
Posts with mentions or reviews of X86-64-semantics.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-01-30.
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Machine readable specifications at scale
I guess I already ran into this argument in practice, with ISAs. For x86 there is an external machine-readable specification (semantics) in the K framework, built by fuzzing and reading the documentation.
riscv-formal
Posts with mentions or reviews of riscv-formal.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-12-10.
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RISC-V simulator
You might be able to hook up your simulator to risc v-formal https://github.com/SymbioticEDA/riscv-formal
- how is to use symbiflow in my fpga projects.
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Machine readable specifications at scale
Then we have RISC, which wrote their own formal verification toolchain here. They just generate Verilog with a Python script. AFAICT this would be really hard to adapt to an assembler. Fortunately the ISA is simple to implement.
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
- Is a single cycle CPU of any use besides learning?
- When to use Formal Verification vs Simulation?
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Where Lions Roam: RISC-V on the VELDT
Your question is certainly not dumb; on the contrary, it is very important! I suppose the developers are responsible for verifying the formal verifier and ensuring it covers the spec. Maybe there is a way to formally verify the formal verifier? Either way, I must give a shout out to the riscv-formal project and its contributors; the project was instrumental to the development of Lion.
Not trying to put words in your mouth, but I do want to clarify something for this audience: the bound in the BMC done by the riscv-formal suite is on the number of cycles, not on the number of bits. Case in point, when you try to BMC the (M)ultiply extensions with the riscv-formal suite, you're actually not allowed to use multiplication because the state space blows up: https://github.com/SymbioticEDA/riscv-formal/blob/master/docs/rvfi.md#alternative-arithmetic-operations
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Any advices for my first RISC-V Core in Verilog ?
Use riscv-formal. It will save a ton of headaches trying to track down a bad instruction. It can generate a module that does checks on the fly during normal sims.
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FPGA and Simulation tools for Risc-V design
I recommend SymbiYosys for formally testing your CPU before ever placing it into a simulation. You can use the riscv-formal property set to get you started, but I'd personally go for an inductive proof of some type and the riscv-formal property set may not get you that far.
What are some alternatives?
When comparing X86-64-semantics and riscv-formal you can also consider the following projects:
hs-arm - (Dis)assembler and analyzer generated from the machine-readable ARMv8.3-A specification
riscv-arch-test
lion - Where Lions Roam: RISC-V on the VELDT
rp32 - RISC-V processor with CPI=1 (every single instruction executed in a single clock cycle).
riscv-tests
Cores-VeeR-EH1 - VeeR EH1 core
autofpga - A utility for Composing FPGA designs from Peripherals
openarty - An Open Source configuration of the Arty platform
simple-riscv - A simple three-stage RISC-V CPU
planckRV32I - Core based on RV32I ISA
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
X86-64-semantics vs hs-arm
riscv-formal vs riscv-arch-test
riscv-formal vs lion
riscv-formal vs rp32
riscv-formal vs riscv-tests
riscv-formal vs Cores-VeeR-EH1
riscv-formal vs autofpga
riscv-formal vs openarty
riscv-formal vs hs-arm
riscv-formal vs simple-riscv
riscv-formal vs planckRV32I
riscv-formal vs VexRiscv