WireHead
riscv-tests
| WireHead | riscv-tests | |
|---|---|---|
| 1 | 9 | |
| 791 | 795 | |
| - | 4.4% | |
| 6.7 | 7.5 | |
| 6 months ago | 3 days ago | |
| C# | C | |
| MIT License | GNU General Public License v3.0 or later |
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WireHead
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Computerraria: A fully compliant RISC-V computer inside Terraria
A friend sent me the YouTube video, which is a fantastic watch: https://www.youtube.com/watch?v=zXPiqk0-zDY.
Minecraft computers have been done for a while now, but seeing a full RISC-V computer running programs is really impressive, and frankly just seems really cool. The programs are written in Rust, and then compiled to run in game. Plus, the author needed to write their own mod to make the Terraria wiring efficient enough to support the computer: https://github.com/misprit7/WireHead
riscv-tests
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Computerraria: A fully compliant RISC-V computer inside Terraria
Fully compliant to RISC-V how? Is it conforming to a specific RVI profile? The project states "By emulating a complete rv32i instruction set inside the wiring system of Terraria, we push back speeds to the early 70s era, tossing the ball firmly back into the court of silicon engineer without losing any software functionality."
So this is building a RISC-V *microcontroller* but what version of the ISA? 2.2 from 2017? Is it sucessfully passing conformance tests (https://github.com/riscv-software-src/riscv-tests)? I don't want to dunk on the project, but the title is over-selling and not scoping the context of the work. I look forward to some more updates from @misprit7!
Note: I'm the working group lead for distro-integration within the RISC-V Software Ecosystem (RISE) group.
- Verification
- Starting my Final Year Project on Architectural Validation of a RISC-V Core
- Efficient Way To Generate Test Benches For MIPS Processor?
- We need some support
- Available (official) test suite?
- Looking for an rv32i asm program that covers all possible scenarios of all instructions for testing
- Compliance tests official repository
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Tips on building a RISC-V processor on FPGA
Always test each of your changes on a battery of tests, like the riscv-tests. Have a way to generate a commit log of instructions and write back values and compare against an ISA simulator like spike or https://github.com/chipsalliance/dromajo.
What are some alternatives?
computerraria - A fully compliant RISC-V computer made inside the game Terraria
riscv-arch-test
dromajo - RISC-V RV64GC emulator designed for RTL co-simulation
riscv-mini - Simple RISC-V 3-stage Pipeline in Chisel
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
riscof
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
riscv-compliance
riscv-formal - RISC-V Formal Verification Framework
simple-riscv - A simple three-stage RISC-V CPU
RISCV-FiveStage - Marginally better than redstone
highway - Performance-portable, length-agnostic SIMD with runtime dispatch