SDRPlusPlus VS corundum

I'm using newest SDR++ nightly built. win x64. Anyone can resolve this problem? Mabye I'm not using the right driver for SDR++? If so where can I find the right one?

SDR++ from GitHub (https://github.com/AlexandreRouma/SDRPlusPlus) runs on M1

Ah, I see what you mean, it's been a while since I looked at their repo. They don't seem to have one for ubuntu jammy yet in their stable release branch. But they do have an ubuntu jammy one in their nightly builds https://github.com/AlexandreRouma/SDRPlusPlus/releases/tag/nightly. I did give it a go and it seems to work okay, but obviously you would need to try it more thoroughly than I have.

What incompatibility? Do you think that this code https://github.com/AlexandreRouma/SDRPlusPlus doesn't support ARM?

SDR++

Some software tips. There is a newer version of SDR++ that includes an IF filter for NOAA APT signals that should help improve things: https://github.com/AlexandreRouma/SDRPlusPlus/releases/tag/nightly That gives you a new checkbox under the Radio section called "IF Noise Reduction" with a dropdown to select the type of reduction (where you select 'NOAA APT'). You can also use the "Decimation" option in the Source section to give a bit better SNR. From what I've read you get a 3db reduction in noise every time you double the decimation level. If you can't get rid of the noise around 137.1MHz maybe try going for NOAA 15 or 18 since those are at higher frequencies, hopefully away from that noise.

The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corundum

Well, I did build this: https://github.com/corundum/corundum

I would look into 10GbE PCS/MAC packet processors implemented under AXI Stream interfaces for example. There are open source examples https://github.com/corundum/corundum and https://netfpga.org/ .

I built my own 100 Gbps capable NIC, along with driver: https://github.com/corundum/corundum. You're welcome to ask if you have any questions, though it is quite a different animal from a 100 Mbps NIC you might have on a microcontroller.

If you're looking for resources, here's one rather comprehensive example of a high-performance FPGA design with a fully custom DMA engine and driver, that runs on both Xilinx and Intel FPGAs: https://github.com/corundum/corundum

I have no idea, but you're welcome to build the design and look at it yourself: https://github.com/corundum/corundum/tree/master/fpga/mqnic/NetFPGA_SUME/fpga. The barrel shifters are in the DMA engine, both the read DMA and write DMA engines have wide barrel shifters.

Dive right into the slack channel and introduce yourself. There is also a new contributor guide. /u/alexforencich/ is on these reddits and he may be able to chime in and give you more concrete suggestions.