vroom VS compiler-explorer

Maybe implement a big feature for a open source design? like vroom or xiangshan.

The two most micro architecturally advanced cores that I know of are BOOM, an out of order RV64GC core with all the features you expect plus sort of weird fancy things like short forward branch predication, and VROOM, another out of order RV64GC core with things like uop fusion and a trace cache.

I had VROOM! in mind (https://github.com/MoonbaseOtago/vroom) because I remembered it aims for 4 IPC avg with a width of 8. Though looking again it's 8 compressed 16 bit instructions or 4 uncompressed 32 bit instruction.

So you could argue a real mix of instructions is not going to be all 16 bit but some 16 and some 32, so the 8 is rarely achieved in practice, and also the block diagram only shows 4 decode blocks. But it can in fact peak at 8 instructions decoded per clock, so I think that qualifies. (You could even argue it's especially impressive, since RISC-V technically qualifies as variable-length encoding like x86, it's just that only 16/32 instructions are really used at the moment)

If you are interested in high performance look into vroom , c910 and xianghan, maybe you could adopt one of them.

On top of what others mentioned (Red Hat) , it is also possible to go with the mysql/mariadb model of dual licensing, you can have a copyleft license where you must contribute back changes, but also allow selling an proprietary license if they want to enhance it but not share the improvements (like amazon or Ampere Computing that enhance ARM designs and sells it for servers), there is already a RISK-V implementation that aims to do that (vroom). another option is a non profit foundation that companies contribute to because they use the project and want it to be better (like the linux foundation) , risc-v has similar nonprofits like the chips alliance (which develops the Rocket-Chip ) or the OpenHW Group (which develops CVA6), there is also lowrisc which develops ibex (but as far as i can tell isn't governed by the contributing companies like the other non profits).

You want a very optimistic answer? someone is working on open source server core, It is already announced and i have been told it is somewhere around four years for a chip to ship after announcement so i would say 4 years from now.

At the moment the Apple M1/M2 are the king of wide decode. Within a couple of years you will see equally wide decode and execute of RISC-V from companies such as Rivos, or indeed open source and GPL'd projects such as VROOM! (https://github.com/MoonbaseOtago/vroom)

> True performance RISCV designs are going to be people's money maker and never open sourced.

That turns out not to be the case.

Alibaba's C910 core -- roughly comparable to the ARM A72 cores (at the same MHz) in the Pi 4 -- is open sourced. It is being used, at 2.5 GHz, in the upcoming "Roma" laptop. That is rather expensive (for now), but I suspect the same TH1520 SoC will quickly find its way onto cheaper SBCs.

There is a very wide OoO GPL'd RISC-V core that is under development. It is aiming for eventual Apple M1 level performance. The current iteration is falling short of that at the moment, but it's already comparable to the ARM A76 in the latest RK3588 SBCs: https://github.com/MoonbaseOtago/vroom

Then you can help open source hardware designs like xiangshan or vroom.

At least on android arm64, looks like a `dmb ishst` is emitted after the constructor, which allows future loads to not need an explicit barrier. Removing `final` from the field causes that barrier to not be emitted.

https://godbolt.org/#g:!((g:!((g:!((h:codeEditor,i:(filename...

You said You won't get "extreme performance" from C++ because it is buried under the weight of decades of compatibility hacks.

Now your whole comment is about vector behavior. You haven't talked about what 'decades of compatibility hacks' are holding back performance. Whatever behavior you want from a vector is not a language limitation.

You could write your own vector and be done with it, although I'm still not sure what you mean, since once you reserve capacity a vector still doubles capacity when you overrun it. The reason this is never a performance obstacle is that if you're going to use more memory anyway, you reserve more up front. This is what any normal programmer does and they move on.

Show what you mean here:

https://godbolt.org/

I've never used ISPC. It's somewhat interesting although since it's Intel focused of course it's not actually portable.

I guess now the goal posts are shifting. First it was that "C++ as a language has performance limitations" now it's "rust has a vector that has a function I want and also I want SIMD stuff that doesn't exist. It does exist? not like that!"

Try to stay on track. You said there were "decades of compatibility hacks" holding back C++ performance then you went down a rabbit hole that has nothing to do with supporting that.

C++ Insights is available online at https://cppinsights.io/

It is also available at a touch of a button within the most excellent https://godbolt.org/

along side the button that takes your code sample to https://quick-bench.com/

Those sites and https://cppreference.com/ are what I'm using constantly while coding.

I recently discovered https://whitebox.systems/ It's a local app with a $69 one-time charge. And, it only really works with "C With Classes" style functions. But, it looks promising as another productivity boost.

[P&H RISC] https://www.google.com/books/edition/_/e8DvDwAAQBAJ

Compiler Explorer by Matt Godbolt [Godbolt] can help better understand what code a compiler generates under different circumstances.

[Godbolt] https://godbolt.org

The official CPU architecture manuals from CPU vendors are surprisingly readable and information-rich. I only read the fragments that I need or that I am interested in and move on. Here is the Intel’s one [Intel]. I use the Combined Volume Set, which is a huge PDF comprising all the ten volumes. It is easier to search in when it’s all in one file. I can open several copies on different pages to make navigation easier.

Intel also has a whole optimization reference manual [Intel] (scroll down, it’s all on the same page). The manual helps understand what exactly the CPU is doing.

[Intel] https://www.intel.com/content/www/us/en/developer/articles/t...

Personally, I believe in automated benchmarks that measure end-to-end what is actually important and notify you when a change impacts performance for the worse.

Let's compile it with https://godbolt.org/, turn on some optimisations and inspect the IR (-O2 -emit-llvm). Copying out the part that corresponds to the while loop:

  4:

resources were extra useful when building deeper intuitions about GPU performance for ML models at work and in graduate school.

- CMU's "Deep Learning Systems" Course is hosted online and has YouTube lectures online. While not generally relevant to software performance, it is especially useful for engineers interested in building strong fundamentals that will serve them well when taking ML models into production environments: https://dlsyscourse.org/

- Compiler Explorer is a tool that allows you easily input some code in and check how the assembly output maps to the source. I think this is exceptionally useful for beginner/intermediate programmers who are familiar with one compiled high-level language and have not been exposed to reading lots of assembly. It is also great for testing how different compiler flags affect assembly output. Many people used to coding in C and C++ probably know about this, but I still run into people who haven't so I share it whenever performance comes up: https://godbolt.org/

To really understand what's going on here we can look at the compiled assembly code. I'm working on a Mac and can do this using the objdump tool. Compiler Explorer is also a handy tool but doesn't seem to support Arm assembly which is what Rust will use when compiling on Apple Silicon.

Play around with it in godbolt if you're really curious: https://godbolt.org/