FPGA-blinky
verilog_template
FPGA-blinky | verilog_template | |
---|---|---|
1 | 1 | |
3 | 0 | |
- | - | |
7.4 | 2.6 | |
3 months ago | 10 months ago | |
Makefile | Makefile | |
GNU General Public License v3.0 or later | - |
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FPGA-blinky
verilog_template
-
(System)Verilog Linting in VSCode?
I have success with iverilog linting! Here is an example project with the settings configured: https://github.com/E4tHam/verilog_template
What are some alternatives?
Makefile_tutor - This project aims to create a crystal clear tutorial on a cryptic looking topic.
Raylib-CPP-Starter-Template-for-VSCODE - Raylib C++ Starter Template for VSCODE
aws-code-habits - A library with Make targets, Ansible playbooks, Jinja templates (and more) designed to boost common software development tasks and enhance governance.
fusesoc_template - Example of how to get started with olofk/fusesoc.
theos - A cross-platform suite of tools for building and deploying software for iOS and other platforms.
vscode-terosHDL - VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!
mxe - MXE (M cross environment)
oss-cad-suite-build - Multi-platform nightly builds of open source digital design and verification tools