Xilinx-DPUV3.0-Vivado-Proj

Deep Learning Processing Unit (DPU IP) integration with Application Processing Unit (APU) using (Zynq-7000 PS) in Xilinx Vivado Design Suite (by mohammadasim98)

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  • DPU on Zynq7000?
    1 project | /r/FPGA | 11 Jun 2022
    Further, I saw a Github project using a Zedboard, which also has the same SoC, and ran the same DPU on it.

Stats

Basic Xilinx-DPUV3.0-Vivado-Proj repo stats
1
3
2.6
over 2 years ago

The primary programming language of Xilinx-DPUV3.0-Vivado-Proj is VHDL.


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