component-template

General SystemVerilog Component Development Template (by NYU-Processor-Design)

Component-template Alternatives

Similar projects and alternatives to component-template

NOTE: The number of mentions on this list indicates mentions on common posts plus user suggested alternatives. Hence, a higher number means a better component-template alternative or higher similarity.

component-template reviews and mentions

Posts with mentions or reviews of component-template. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2024-03-07.
  • Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud
    6 projects | news.ycombinator.com | 7 Mar 2024
    The functionality on offer here is equivalent to about 30 lines of Github Actions YAML to install verilator, run the tests, and upload the coverage information. [1]

    Generating waveforms is free, Verilator already does that if you pass it the appropriate argument, either --trace or --trace-fst. We usually control that with a single CMake option.

    Complex workflows can get nutty, but what's illustrated here is not a complex workflow.

    [1]: https://github.com/NYU-Processor-Design/component-template/b...

Stats

Basic component-template repo stats
1
0
3.9
3 months ago

NYU-Processor-Design/component-template is an open source project licensed under Creative Commons Zero v1.0 Universal which is not an OSI approved license.

The primary programming language of component-template is CMake.


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