component-template
PurdNyUart
| component-template | PurdNyUart | |
|---|---|---|
| 1 | 2 | |
| 0 | 1 | |
| - | - | |
| 3.9 | 7.5 | |
| 3 months ago | 3 months ago | |
| CMake | SystemVerilog | |
| Creative Commons Zero v1.0 Universal | Creative Commons Zero v1.0 Universal |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
component-template
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Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud
The functionality on offer here is equivalent to about 30 lines of Github Actions YAML to install verilator, run the tests, and upload the coverage information. [1]
Generating waveforms is free, Verilator already does that if you pass it the appropriate argument, either --trace or --trace-fst. We usually control that with a single CMake option.
Complex workflows can get nutty, but what's illustrated here is not a complex workflow.
[1]: https://github.com/NYU-Processor-Design/component-template/b...
PurdNyUart
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Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud
This is my feeling too, it's pretty trivial to do this stuff in git CI.
At NYU we have this entire process built into very trivial CMake and Github Actions stuff.
Here's an example: https://github.com/NYU-Processor-Design/PurdNyUart
You can see we have 100% test coverage, illustrated by CodeCov, and our CI runs the test suite on each PR. This is very normal in the software world and I guess I don't understand why the hardware world would need a specialized provider just to run Verilator for you.
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C++ Verification Testbench Best-Practice Resources?
Here's a test bench a Baudrate Generator.
What are some alternatives?
nyu-util - Utilities for the NYU ProcDesign team
r5lite