component-template
General SystemVerilog Component Development Template (by NYU-Processor-Design)
GettingVerilatorStartedWithUVM
Simple UVM environment for experimenting with Verilator. (by MikeCovrado)
| component-template | GettingVerilatorStartedWithUVM | |
|---|---|---|
| 1 | 1 | |
| 0 | 6 | |
| - | - | |
| 3.9 | 5.3 | |
| 3 months ago | 6 months ago | |
| CMake | SystemVerilog | |
| Creative Commons Zero v1.0 Universal | Apache License 2.0 |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
component-template
Posts with mentions or reviews of component-template.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-07.
-
Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud
The functionality on offer here is equivalent to about 30 lines of Github Actions YAML to install verilator, run the tests, and upload the coverage information. [1]
Generating waveforms is free, Verilator already does that if you pass it the appropriate argument, either --trace or --trace-fst. We usually control that with a single CMake option.
Complex workflows can get nutty, but what's illustrated here is not a complex workflow.
[1]: https://github.com/NYU-Processor-Design/component-template/b...
GettingVerilatorStartedWithUVM
Posts with mentions or reviews of GettingVerilatorStartedWithUVM.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-03-07.
-
Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud
I noticed there are some GitHub Repos active on enabling UVM on Verilator:
https://github.com/MikeCovrado/GettingVerilatorStartedWithUV...
It would be an amazing leap to enable UVM fully on Verilator. Looking forward to it.