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SPI-Register-Access-Controller
Here you can find the RTL for a SPI+Register bank controller which can be used to test stand-alone Analog/Digital IP
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InfluxDB
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Not really, for the interface logic you only need two shift registers and one counter. for example, here I did it in less than 100 lines of verilog: https://github.com/Askartos/SPI-Register-Access-Controller/blob/main/rtl/src/main/resources/spi.v
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