Generating video timing signals using VHDL

• HDMI_testikuva

  3 11 0.0 Verilog

  Sipeed Tang Nano 4K FPGA implementation of the static tuning picture I watched on TV as a kid.

There are several resources on the web on how to generate a display signal, also a good number of different code examples. Here is a compact one I wrote in Verilog a way back: https://github.com/juj/HDMI_testikuva/blob/master/src/display_signal.v , maybe that might be easy to adapt to VHDL?

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