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This is dope. I work with Zynq/Versal quite a bit and respect and understand (conceptually) the decisions you have made!
You get to own every aspect of your toolchain and with that will come a lot of power.
Are you familiar with:
https://github.com/corundum/corundum
Perhaps you can build a support package for your platform.
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imxrt-level2-boot
Build secondary bootloader for NXP i.MXRT series | 一个基于i.MXRT的二级boot设计，主要用于加载app启动，不涉及下载更新app
> I have some RT1176's in my "to try" pile.
Keep in mind the dual-core 11xx chips are a bit harder to boot than the rest of the line - but you probably need the power domain flexibility for most FPGA projects (1064 has way fewer practically-usable 1v8 banks.)
> crypto accelerators were all locked behind NDAs
I've been able to use every bit of hard IP and high-assurance boot from registers using no vendor code whatsoever.
Here's what you are looking for:
https://github.com/JayHeng/imxrt-level2-boot/blob/master/dev...
> The other issue I had with the RT is that they lacked internal flash
The IMXRT1064 has a 4MB Winbond QSPI chip in-package, by the way!
> PCB complexity is slightly higher than with a STM32.
The Xilinx FPGA that is sitting next to your MCU incurs multiple orders of magnitude more PCB-complexity than a little QSPI flash, haha.
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> Can the Zynq 7010 handle something like data transfer from a 4K image sensor to a USB 3 transceiver?
The Zynq 7010 is less-than-ideal for this because you'd have to use some kind of USB3 interface PHY - which would increase cost and be pretty limited functionality-wise.
If you use an FPGA with transceivers (some 7 series Artix chips - https://www.lcsc.com/product-detail/Programmable-Logic-Devic..., most 7 series Virtex/Kintex chips, all US/US+ chips), you can implement USB3 without an external PHY: https://github.com/enjoy-digital/usb3_pipe
The Z7010 probably has the area to do this type of translation but not the transceivers. There are other chips in the 7 series Zynq family with capable transceivers, but they are much more expensive ($15-$35 from CN).
> I was under the impression the PIO has fairly precise timing if you set up your clocks right, but maybe I've been misled here.
No measured data, but when I was once implementing JTAG and SPI at 50MHz+ with an extremely overclocked chip, the edges were very inconsistent in relation to each other and in pulse width - 5-15ns (estimating from memory, they were sloppy.)
