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why not just load a 6502 soft core into the fpga
a 6502 is about 1200 gates i think, which is very roughly 400 4-luts
https://github.com/emeb/ulx3s_6502 simulates a 6502 on a lattice ecp5, using yosys, nextpnr, and the well-known (apparently! i'd never heard of it) https://github.com/Arlet/verilog-6502
why not just load a 6502 soft core into the fpga
a 6502 is about 1200 gates i think, which is very roughly 400 4-luts
https://github.com/emeb/ulx3s_6502 simulates a 6502 on a lattice ecp5, using yosys, nextpnr, and the well-known (apparently! i'd never heard of it) https://github.com/Arlet/verilog-6502