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Not really, at least not apples-apples for something like a Pi.
There are a couple of different aspects to this, one is that soft-logic it typically slower than hard-logic so you just can't get comparable frequencies out of a soft implementation. For datapath designs, this is typically solved by going wider, but that isn't quite as helpful or practical for all aspects of a processor implemented in soft logic.
If you look at the specs for this softcore processor, they have much less performance than a Pi, even when you're using some of the biggest and more $$ families of FPGAs: https://www.xilinx.com/products/design-tools/microblaze.html....
I'd say that is on-part with similar complexity soft-core CPUs from other vendors or even open-source ones.
With respect to the design transparency, it kind of depends on how much you care about the black-box compilers required to use a lot of these advanced chips. You can feed open-source RTL into them, but there's still a proprietary black-box compiler/fitter/place-route etc for a lot of these.
There's some work toward open toolchains from yosys and https://f4pga.org/, but none of the big FPGA companies seem very bought-in or willing to help a, so it's been a community best-effort, and for some of the fancier devices, you still have to use the proprietary tools to build bitstreams.