cascade VS AutoSA

Compare cascade vs AutoSA and see what are their differences.

cascade

A Just-In-Time Compiler for Verilog from VMware Research (by vmware-archive)

AutoSA

AutoSA: Polyhedral-Based Systolic Array Compiler (by UCLA-VAST)
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cascade AutoSA
1 3
422 176
- 5.1%
0.6 0.0
almost 3 years ago over 1 year ago
C++ C++
GNU General Public License v3.0 or later MIT License
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.

cascade

Posts with mentions or reviews of cascade. We have used some of these posts to build our list of alternatives and similar projects. The last one was on 2022-05-23.
  • Who would benefit if there were an FPGA-only linux OS.
    3 projects | /r/FPGA | 23 May 2022
    I think VMWare did a just-in-time compilation for verilog called Cascade that I don't think ever got a lot of traction that seems to do parts of what you are looking for in that code first gets executed in a simulator until hardware-compilation is done in which case it is automatically migrated to the hardware/accelerated version. Sadly, the tool/project seems to have been shelved by VMWare and development has moved out into original author's private repo which I think itself may say something about the idea.

AutoSA

Posts with mentions or reviews of AutoSA. We have used some of these posts to build our list of alternatives and similar projects.

What are some alternatives?

When comparing cascade and AutoSA you can also consider the following projects:

DomesdayDuplicator - High-speed LaserDisc RF sampler