ulx3s_6502
Simple 6502 system on a ULX3S FPGA board (by emeb)
verilog-6502
A Verilog HDL model of the MOS 6502 CPU (by Arlet)
ulx3s_6502 | verilog-6502 | |
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1 | 2 | |
16 | 310 | |
- | - | |
10.0 | 1.1 | |
about 4 years ago | about 1 year ago | |
Verilog | Verilog | |
- | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
ulx3s_6502
Posts with mentions or reviews of ulx3s_6502.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-01-09.
-
An Easy to Build Real Homemade Computer: Z80-MBC2
why not just load a 6502 soft core into the fpga
a 6502 is about 1200 gates i think, which is very roughly 400 4-luts
https://github.com/emeb/ulx3s_6502 simulates a 6502 on a lattice ecp5, using yosys, nextpnr, and the well-known (apparently! i'd never heard of it) https://github.com/Arlet/verilog-6502
verilog-6502
Posts with mentions or reviews of verilog-6502.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2024-01-09.
-
An Easy to Build Real Homemade Computer: Z80-MBC2
why not just load a 6502 soft core into the fpga
a 6502 is about 1200 gates i think, which is very roughly 400 4-luts
https://github.com/emeb/ulx3s_6502 simulates a 6502 on a lattice ecp5, using yosys, nextpnr, and the well-known (apparently! i'd never heard of it) https://github.com/Arlet/verilog-6502
- What is the simplest CPU (That will run BASIC) to make in a digital logic sim?