tomverbeure
By tomverbeure
vexriscv_ocd
By tomverbeure
| tomverbeure | vexriscv_ocd | |
|---|---|---|
| 5 | 3 | |
| - | 2 | |
| - | - | |
| - | 6.1 | |
| - | almost 3 years ago | |
| Assembly | ||
| - | - |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
tomverbeure
Posts with mentions or reviews of tomverbeure.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-04-16.
- so the timing generator seems to work ok...
-
Where to get started?
Here are some of my unpublished notes on how to install the software. Maybe it’s helpful to you?
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How to debug a RISC-V soft core
I’m in the process of writing a blog post about debugging a VexRiscv soft core. It’s work in progress, but the introduction should give you an idea how things connect together in general.
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Has anyone had any experience with this ultra-cheap Chinese FPGA board - the Sipeed Tang Nano
I never finished a blog post about it, but here are the notes that I made along the way about installing the tools etc.
- Digilent JTAG HS3 - Altera
vexriscv_ocd
Posts with mentions or reviews of vexriscv_ocd.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-05-23.
-
Weird altera issue
My VexRiscv design with this QSF file works find for me: https://github.com/tomverbeure/vexriscv_ocd/blob/intel/verilog_example/quartus_max10_deca/vexriscv_ocd.qsf.
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console-like interface to dev board through built-in USB?
create your design and add an Intel JTAG UART IP. You can copy it from my design or you can create one with Quartus Qsys.
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How to debug a RISC-V soft core
Similarly, my the README of test project might give you some pointers.
What are some alternatives?
When comparing tomverbeure and vexriscv_ocd you can also consider the following projects:
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.
riscv-debug-spec - Working Draft of the RISC-V Debug Specification Standard
apicula - Project Apicula 🐝: bitstream documentation for Gowin FPGAs
VexRiscv - A FPGA friendly 32 bit RISC-V CPU implementation
ibex - Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.