Weird altera issue

• VexRiscv

  21 2,269 7.3 Assembly

  A FPGA friendly 32 bit RISC-V CPU implementation

  

I'm trying to put the Murax SoC inside a DECA board from Arrow but I'm facing something quite odd. Along with the SoC, I'm adding a heartbeat LED just in case to see if everything is running and what I'm seeing is that when I try to constraint the jtag pins, starting by the TDI (Y5) on the SDC file, the bitstream programmed in the board makes the heartbeat LED to stop blink (it stucks on forever). In the beginning, I was thinking that would be something related to the voltage but as the pins C5-LED and Y5-TDI are from different banks, it doesn't make any sense....is there something I'm missing from here?

• vexriscv_ocd

  3 2 6.1 Assembly

My VexRiscv design with this QSF file works find for me: https://github.com/tomverbeure/vexriscv_ocd/blob/intel/verilog_example/quartus_max10_deca/vexriscv_ocd.qsf.

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