stm32-hal VS cortex-m

Typestate-free HALs: This is in exchange for better ergonomics as the author claims. Only two HALs fall in this category right now which are the STM32-HAL & nRF-HAL.

As I worked with the stm32, as implied earlier, the HALs that I worked with were ones built around embedded-hal traits. Nevertheless, I came across a HAL at a certain point that adopted a different approach that felt more practical and easy to understand. This was the stm32-hal stm32-hal that I found to be more wholesome as it incroporated multiple families of the STM32 under a single HAL umbrella (my original expectation). The STM32-hal eliminates much of the trait confusion that I had encountered before. The thing is the stm32-hal does not seem to be mainstream yet. From what I understand, the HALs built with the mebedded-hal as a basis seem to be the ones mainly adopted by the embedded working group. Additionally, I am not sure if the stm32-hal has any equivalent counterparts for other manufacturer devices.

📝 At the time of writing this post, it came to my attention that there is an additional HAL that targets STM32 device families (the stm32-hal). From what I figure, right now there seem to be two approaches for developing HALs. The first approach is trait driven so to speak where the embedded-hal is used as a foundation. The second approach is more application-driven and provides a high-level API that targets several families of a device. However, this exists only for the stm32 through the stm32-hal. Right now, the first approach is what I found to be more widespread as it covers different microcontrollers and what this post is based on.

For STM32, check out the Peripheral Access Crates by the stm32-rs ream. For higher-level access, I wrote This HAL library for STM32. Works on most newer variants, and includes examples for specific peripherals, and simple applications.

I do not have as strong of feelings as your parent, but:

1. A lot of the APIs make use of the typestate pattern, which is nice, but also very verbose, and might turn many people off.

2. The generated API documentation for the lower level crates relies on you knowing the feel for how it generates the various APIs. It can take some time to get used to, especially if you're used to the better documentation of the broader ecosystem.

3. A bunch of the ecosystem crates assume the "I am running one program in ring0" kind of thing, and not "I have an RTOS" sort of case. See the discussion in https://github.com/rust-embedded/cortex-m/issues/233 for example.

For cortex-m support, check out the cortex-m crate

See https://github.com/rust-embedded/cortex-m/tree/master/panic-semihosting

I don't think so. Once a function is compiled, it basically becomes a black box with a type signature so unless sleeping in a function affects its signature, that information is erased. If you pass in some kind of a sleep token that has to be used to sleep, then yeah I think you could enforce it by only being able to get that token in a non-atomic context and making it leak proof.

The Cortex-M crate does something similar, but for proving that you are in an atomic context. Another function that expects a CriticalSection type is then assured that it's running without interrupts enabled.

https://github.com/rust-embedded/cortex-m/blob/master/src/in...