satcat5
fiate
satcat5 | fiate | |
---|---|---|
25 | 4 | |
390 | 7 | |
10.5% | - | |
3.8 | 0.0 | |
2 months ago | over 2 years ago | |
VHDL | VHDL | |
CERN Open Hardware Licence Version 2 - Weakly Reciprocal | Apache License 2.0 |
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satcat5
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Layout of Rust's u128 and i128 changed
I needed 128-bit and 256-bit integers on an embedded project recently.
In short, it was for fixed-point digital signal processing. The raw input and output samples were int64_t. We needed to add, subtract, multiply, and accumulate these to do filtering and linear regression with no loss of precision.
Conventional bigintegers weren't an option because the target application doesn't allow heap allocation. So we rolled our own [1] stack-allocated, fixed-width big integer class.
[1] https://github.com/the-aerospace-corporation/satcat5/blob/ma...
- Show HN: SatCat5, the open-source FPGA Ethernet switch
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CRC32 algorithm match value between 96 bit wide data bus and 24 bit wide data bus
And here's an open-source implementation I wrote a few years back. You can skip the part at the end that handles variable-length trailing bytes, since you have a fixed-width input.
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Questions about lattice ecp5 fpga.
My SatCat5 project also has a few options. Anything under src/vhdl/common/cfgbus_* can be connected to AXI or Wishbone with a simple adapter.
- SatCat5: FPGA gateware that implements a low-power, mixed-media Ethernet switch
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GPSDO without VCXO?
For an all-digital solution, here's an NCO that generates an arbitrary-frequency square wave from a numeric counter.
- network switch
fiate
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Building xvc_pup device drivers from the source.
Try this: https://github.com/byuccl/fiate/blob/main/host_sw/xvc.py There are other GitHub examples as well. https://github.com/search?q=xilinx+virtual+cable
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Help setting up Xilinx Artix-7 FPGA (RHS Labs Litefury FPGA board)
Here is my Github work with the SQRL Acorn (same design as the litefury): https://github.com/byuccl/fiate
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SPI flash command set specification
I have that part in a few SQRL acorn FPGAs. Here is my python wrapper for the Xilinx QSPI device. https://github.com/byuccl/fiate/blob/main/host_sw/qspi.py
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
What are some alternatives?
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SpinalHDL - Scala based HDL
surf - A huge VHDL library for FPGA development
WARP_Core - Wilson AXI RISCV Processor Core
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
opentitan - OpenTitan: Open source silicon root of trust
litex - Build your hardware, easily!
chisel - Chisel: A Modern Hardware Design Language
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images