riscv-sbi-doc
riscv-uefi
| riscv-sbi-doc | riscv-uefi | |
|---|---|---|
| 5 | 2 | |
| 316 | 21 | |
| 2.2% | - | |
| 7.5 | 10.0 | |
| 26 days ago | almost 2 years ago | |
| Makefile | Makefile | |
| Creative Commons Attribution 4.0 | Creative Commons Attribution 4.0 |
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riscv-sbi-doc
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RISC-V SBI and the full boot process
The SBI spec[0] is not a long read.
0. https://github.com/riscv-non-isa/riscv-sbi-doc/releases
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ARM or x86? ISA Doesn’t Matter
>What does matter is standardization. For example a booting process.
Truth.
This is why RISC-V put a lot of effort on this, and put it early.
Relevant specs include but isn't limited to SBI[0], UEFI protocol[1] and the ongoing platform specification[2].
0. https://github.com/riscv-non-isa/riscv-sbi-doc/releases
1. https://github.com/riscv-non-isa/riscv-uefi/releases/tag/1.0...
2. https://github.com/riscv/riscv-platform-specs
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HiFive Unmatched – A RISC-V Linux development platform
Well that's a very good question. At the moment the reality is something of a mess, because someone looked at Arm and though that must be a good idea. Plus the RISC-V Foundation has even less control over implementers than Arm does (which doesn't have a lot).
The good news is that the foundation is defining various platform specs. For servers it'll include a standard firmware spec plus open source firmware implementation and a few other bits. Maybe working UEFI one day. (https://lists.riscv.org/g/tech-unixplatformspec https://github.com/riscv-non-isa/riscv-sbi-doc)
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what is EEI, AEE, SEE, SBI? How do they all fit together?
The SBI (Supervisor-Binary Interface) is the API used by S-mode software (your operating system) to communicate with M-mode, and abstract away some hardware-specific details. It handles things like communicating between harts, power management, and performance monitoring. On real hardware, it is implemented by M-mode software. For VMs, it is typically implemented by the hypervisor. It's roughly analogous to the PSCI in ARM. For more information, have a look at the spec.
riscv-uefi
- StarFive VisionFive 2 SBC Now Supports TianoCore EDK II (UEFI)
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ARM or x86? ISA Doesn’t Matter
>What does matter is standardization. For example a booting process.
Truth.
This is why RISC-V put a lot of effort on this, and put it early.
Relevant specs include but isn't limited to SBI[0], UEFI protocol[1] and the ongoing platform specification[2].
0. https://github.com/riscv-non-isa/riscv-sbi-doc/releases
1. https://github.com/riscv-non-isa/riscv-uefi/releases/tag/1.0...
2. https://github.com/riscv/riscv-platform-specs
What are some alternatives?
riscv-bitmanip - Working draft of the proposed RISC-V Bitmanipulation extension
riscv-platform-specs - RISC-V Profiles and Platform Specification
nytm-spelling-bee - Generate anagram puzzles like Frank Longo's "Spelling Bee" as in New York Times Magazine
vroom - VRoom! RISC-V CPU
edk2
riscv-acpi
riscv-bringup - Risc-V journey thru containers and new projects