riscv-gnu-toolchain
Ripes
| riscv-gnu-toolchain | Ripes | |
|---|---|---|
| 35 | 18 | |
| 3,121 | 2,368 | |
| 2.2% | - | |
| 8.2 | 7.2 | |
| 7 days ago | 27 days ago | |
| C | C++ | |
| GNU General Public License v3.0 or later | MIT License |
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riscv-gnu-toolchain
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Is RISC-V ready for HPC? Evaluating the 64-core Sophon SG2042 RISC-V CPU
> no absurdely and grotesquely massive and complex compilers anywhere
Absence of evidence is not evidence of absence, and anyway there's not even an absence: https://github.com/riscv-collab/riscv-gnu-toolchain https://llvm.org/docs/RISCVUsage.html
> feature creeps on computer language syntax nowhere to be found
At least one of us is very confused, and in case it's me, how do language details matter to RISC-V?
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Help trying to build for riscv64gc-unknown-linux-musl
I then looked at the .cargo/config.toml provided by the guide and saw that it wasn't actually statically compiling the code. After a bit of tinkering and building my own toolchain from here, I ended up with this config.toml file:
- GNU toolchain for RISC-V including GCC
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Building a toolchain suitable for compiling V extension code
b) collabriscv - essentially gcc 12.2 + binutils master/2.40 as per https://github.com/riscv-collab/riscv-gnu-toolchain
- How do i specify vendor name while building the GNU toolchain?
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GCC 13 Adds RISC-V T-Head Vendor Extension Collection
Or would it be better to take what is in https://github.com/riscv-collab/riscv-gnu-toolchain which is gcc 12.2 and start from there?
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How to build toolchain with Zbs extension?
I'm not able to build https://github.com/riscv-collab/riscv-gnu-toolchain.git like this:
Ripes
- Web GUI for the Ripes RISC-V simulator
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C++ or Rust after having learnt C ?
Are you talking about projects such as this? https://github.com/mortbopet/Ripes
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Hardware/software to run RISC-V ASM?
If you want to see more what is going on under the hood of a RISC-V CPU you could use the graphical simulator Ripes: https://github.com/mortbopet/Ripes
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Open-source RISC-V simulator suggestions?
https://github.com/mortbopet/Ripes is in c++
- Ripes: Visual computer architecture simulator, assembly code editor for RISC-V
- Emulator (not qemu) for learning risc-v without Just In Time execution?
- Compiling RV32I assembly without C in Freedom?
What are some alternatives?
riscv-binutils-gdb - RISC-V backports for binutils-gdb. Development is done upstream at the FSF.
rars - RARS -- RISC-V Assembler and Runtime Simulator
risc-v-examples - RISC-V examples for GD32V, K210, and QEMU
riscv_vhdl - Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators
rvv-llvm - This repository is outdated, support for RISC-V is now developed in upstream LLVM
jupiter - RISC-V Assembler and Runtime Simulator
buildroot - Buildroot, making embedded Linux easy. Note that this is not the official repository, but only a mirror. The official Git repository is at http://git.buildroot.net/buildroot/. Do not open issues or file pull requests here.
nightmare
freedom-tools - Tools for SiFive's Freedom Platform
awesome-hdl - Hardware Description Languages
xv6-riscv - Xv6 for RISC-V
Kite - Kite: Architecture Simulator for RISC-V Instruction Set