red-pitaya-notes
Vitis_Accel_Examples
red-pitaya-notes | Vitis_Accel_Examples | |
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1 | 3 | |
316 | 468 | |
- | 1.7% | |
9.0 | 8.0 | |
about 2 months ago | 4 months ago | |
Tcl | Makefile | |
MIT License | MIT License |
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red-pitaya-notes
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Share data with PL from PS ( Petalinux)
configuration register module with AXI4-Lite slave interface and with a configurable number of addressable registers (FDRE). The output of each register can be individually connected to ports of other modules and output pins. If you do not need more than 32 bits of configuration registers, then AXI GPIO can be also used in a similar way.
Vitis_Accel_Examples
- Can you help me dataflow checking failure on vitis hls?
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How to Implement a decision tree on FPGA?
3- Then in Vitis I have implement that if-else statement to build the hardware. I have taken this Vitis hello world example as reference to write code for decision tree.
- Design AXI4 MM -> S and S -> MM
What are some alternatives?
cariboulite - CaribouLite turns any 40-pin Raspberry-Pi into a Tx/Rx 6GHz SDR
XRT - Run Time for AIE and FPGA based platforms
Skywave-Linux-v4 - Scripts providing efficient, powerful, yet user friendly software defined radio operation in Skywave Linux v4
hlslib - A collection of extensions for Vitis and Intel FPGA OpenCL to improve developer quality of life.
Vitis-Tutorials - Vitis In-Depth Tutorials
cordic - A series of CORDIC related projects
Alveo-PYNQ - Introductory examples for using PYNQ with Alveo
ticklecharts - Tcl wrapper around Apache ECharts.
c8hardcaml - An implementation of a CHIP-8 machine for FPGAs in Hardcaml with a custom assembler for writing test programs
SoC - Github Repo for Embedded FPGA course by Vincent Claes
acap3-examples - Example code for APIs and features in AXIS Camera Application Platform (ACAP) version 3