r5lite
PurdNyUart
| r5lite | PurdNyUart | |
|---|---|---|
| 2 | 2 | |
| - | 1 | |
| - | - | |
| - | 7.5 | |
| - | 3 months ago | |
| SystemVerilog | ||
| - | Creative Commons Zero v1.0 Universal |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
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r5lite
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Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud
It's not in gitlab's CI infrastructure, but I have continuous integration set up in a private server for https://gitlab.com/specbranch/r5lite and also for my company's proprietary hardware.
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Recommendations for RISC-V on FPGA
I wish I could recommend the one I am working on open-sourcing, but it's not exactly ready yet for a school project (shameless plug for the future: https://gitlab.com/specbranch/r5lite/) unless you are doing something very basic solely inside the core.
PurdNyUart
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Launch HN: SiLogy (YC W24) – Chip design and verification in the cloud
This is my feeling too, it's pretty trivial to do this stuff in git CI.
At NYU we have this entire process built into very trivial CMake and Github Actions stuff.
Here's an example: https://github.com/NYU-Processor-Design/PurdNyUart
You can see we have 100% test coverage, illustrated by CodeCov, and our CI runs the test suite on each PR. This is very normal in the software world and I guess I don't understand why the hardware world would need a specialized provider just to run Verilator for you.
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C++ Verification Testbench Best-Practice Resources?
Here's a test bench a Baudrate Generator.
What are some alternatives?
iob-soc - RISC-V System on Chip Template
nyu-util - Utilities for the NYU ProcDesign team
neorv32 - :rocket: A tiny, customizable and extensible MCU-class 32-bit RISC-V soft-core CPU and microcontroller-like SoC written in platform-independent VHDL.
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux