ara
snitch
ara | snitch | |
---|---|---|
5 | 4 | |
304 | 210 | |
2.0% | - | |
7.5 | 0.0 | |
21 days ago | 5 months ago | |
C | SystemVerilog | |
GNU General Public License v3.0 or later | Apache License 2.0 |
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ara
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x86 vs ARM; Vector and Matrix Extensions; How do they compare?
yeah, ara also currently doesn't work, but that it exist is already really cool, and will likely get fixed and completed in the future
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Ara2: RVV 1.0 Compliant Open-Source Processor
The ISA is variable length/scalable, but this implementation uses a 4096 wide register file.
They are a bit disingenuous in claiming they support rvv 1.0 while others only a subset, as they haven't implemented vrgather or vcompress yet, but there are open pull request for them [0].
Sadly there also seem to be a few bugs when simulating with verilator [1], so I couldn't measure all instructions, but here is `vadd.vv` and `vwaddu.vv` for the VLEN=4096, four lane configuration:
vadd.vv:
e32m1: 16 cycles
e32m2 32 cycles
e32m4 63 cycles
e32m8 126 cycles
vwaddu.vv:
e32m1: 34 cycles
e32m2: 69 cycles
e32m4: 140 cycles
[0] https://github.com/pulp-platform/ara/pull/180
[1] https://github.com/pulp-platform/ara/issues/250
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432-Core Chiplet-Based RISC-V Chip Nearly Ready to Blast Into Space
The PULP Ara is a 64-bit Vector Unit
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Iām not expert, but I guess it is worth to check out
It's not made very clear until the Conclusion section that they have provided an open source implementation of a RVV 1.0 vector unit, available at https://github.com/pulp-platform/ara : "The PULP Ara is a 64-bit Vector Unit, compatible with the RISC-V Vector Extension Version 1.0, working as a coprocessor to CORE-V's CVA6 core."
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Yun, the first tape-out of CVA6 (Ariane) with Ara vector co-processor SoC manufactured
The source code of Ara as well as Ariane, also known as CVA6 is available on GitHub.
snitch
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432-Core Chiplet-Based RISC-V Chip Nearly Ready to Blast Into Space
Btw the Snitch-cluster used in Occamy is open-source, you can find the code here: https://github.com/pulp-platform/snitch
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432-Core RISC-V European Processor Designed for Use in Space Taped Out
More details here: https://pulp-platform.org/docs/STW2022_kgf.pdf
Here's the source for the data plane CPU core: https://github.com/pulp-platform/snitch
- Banshee: A Fast LLVM-Based RISC-V Binary Translator [pdf]
What are some alternatives?
cva6 - The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
simd_utils - A header only library implementing common mathematical functions using SIMD intrinsics
esp - Embedded Scalable Platforms: Heterogeneous SoC architecture and IP integration made easy
riscv-ocelot - Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
Unicorn Engine - Unicorn CPU emulator framework (ARM, AArch64, M68K, Mips, Sparc, PowerPC, RiscV, S390x, TriCore, X86)