prjtrellis
6502-exp
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| prjtrellis | 6502-exp | |
|---|---|---|
| 5 | 1 | |
| 381 | 0 | |
| 0.0% | - | |
| 8.5 | 10.0 | |
| 3 months ago | about 3 years ago | |
| Python | Assembly | |
| GNU General Public License v3.0 or later | - |
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prjtrellis
- Project Trellis – Documenting the Lattice ECP5 FPGA Bitstream Format
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Learning Verilog and FPGA
Yosys, the underlying compiler of ice studio, also targets the much bigger ECP5 FPGA, also by Lattice, which is called Project Trellis: https://github.com/YosysHQ/prjtrellis
Yosys functions more like a software open source tool. So command line compiling. It also has a REPL. It is very quick compared to the commercial solutions. Especially around compile times which can take seconds instead of minutes. YMMV, but I think the consensus is that it's a lot more convenient to use.
In general the hardware toolchains feel very ancient compared to software toolchains.
- Project Trellis – fully open-source flow for ECP5 FPGAs, using Yosys and nextpnr
- 5% of 666 Python repos had comma typo bugs (inc V8, TensorFlow and PyTorch)
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Lattice ECP3 - any way of working withe them with free license ?
Not that it will lead to anything soon, you could put a feature request in at Project Trellis and offer to test things, or provide hardware if you have extra.
6502-exp
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Learning Verilog and FPGA
Chisel is compiled to Verilog so it has excellent interoperability. You can use Chisel in an existing Verilog project or use existing Verilog modules in a Chisel project. Therefore it is already supported by practically all vendors and simulators.
I've used Chisel to interface with proprietary Lattice DSPs and RAM modules, and I'm sure you could do the same with other vendors as well. All you have to do is define the IOs and parameters of the module. In Chisel this is called a "Blackbox". Example: https://github.com/fayalalebrun/6502-exp/blob/master/src/mai...
What are some alternatives?
Vulkan-ValidationLayers - Vulkan Validation Layers (VVL)
apio - :seedling: Open source ecosystem for open FPGA boards
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
prince - The Prince lightweight block cipher in Verilog.
quickstep - Quickstep project
f4pga-arch-defs - FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
vhdl-tutorial
Keras - Deep Learning for humans