fiate
Fault Injection Automatic Test Equipment (by byuccl)
BYU_PYNQ_PR_Video_Pipeline
The Demo that was presented at FCCM. (by byuccl)
| fiate | BYU_PYNQ_PR_Video_Pipeline | |
|---|---|---|
| 4 | 2 | |
| 7 | 14 | |
| - | - | |
| 0.0 | 0.0 | |
| over 2 years ago | over 5 years ago | |
| VHDL | Jupyter Notebook | |
| Apache License 2.0 | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
fiate
Posts with mentions or reviews of fiate.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-14.
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Building xvc_pup device drivers from the source.
Try this: https://github.com/byuccl/fiate/blob/main/host_sw/xvc.py There are other GitHub examples as well. https://github.com/search?q=xilinx+virtual+cable
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Help setting up Xilinx Artix-7 FPGA (RHS Labs Litefury FPGA board)
Here is my Github work with the SQRL Acorn (same design as the litefury): https://github.com/byuccl/fiate
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SPI flash command set specification
I have that part in a few SQRL acorn FPGAs. Here is my python wrapper for the Xilinx QSPI device. https://github.com/byuccl/fiate/blob/main/host_sw/qspi.py
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
BYU_PYNQ_PR_Video_Pipeline
Posts with mentions or reviews of BYU_PYNQ_PR_Video_Pipeline.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-11-15.
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References for video system design on FPGAs.
Here is my example: Thesis: https://scholarsarchive.byu.edu/etd/8620/ HW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline_Hardware SW: https://github.com/byuccl/BYU_PYNQ_PR_Video_Pipeline
- Share some github FPGA projects (bonus if they include C++, Python, or other files)
What are some alternatives?
When comparing fiate and BYU_PYNQ_PR_Video_Pipeline you can also consider the following projects:
verilog-ethernet - Verilog Ethernet components for FPGA implementation
SpinalHDL - Scala based HDL
WARP_Core - Wilson AXI RISCV Processor Core
corundum - Open source FPGA-based NIC and platform for in-network compute
satcat5 - SatCat5 is a mixed-media Ethernet switch that lets a variety of devices communicate on the same network.
verilog-wishbone - Verilog wishbone components
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
litex - Build your hardware, easily!
FPGA_RealTime_and_Static_Sobel_Edge_Detection - Pipelined implementation of Sobel Edge Detection on OV7670 camera and on still images
fiate vs verilog-ethernet
BYU_PYNQ_PR_Video_Pipeline vs verilog-ethernet
fiate vs SpinalHDL
BYU_PYNQ_PR_Video_Pipeline vs SpinalHDL
fiate vs WARP_Core
BYU_PYNQ_PR_Video_Pipeline vs corundum
fiate vs satcat5
BYU_PYNQ_PR_Video_Pipeline vs verilog-wishbone
fiate vs SBusFPGA
BYU_PYNQ_PR_Video_Pipeline vs satcat5
fiate vs litex
BYU_PYNQ_PR_Video_Pipeline vs FPGA_RealTime_and_Static_Sobel_Edge_Detection