eth10g
10Gb Ethernet Switch (by ZipCPU)
demo-projects
Demo projects for various Kintex FPGA boards (by openXC7)
| eth10g | demo-projects | |
|---|---|---|
| 2 | 1 | |
| 135 | 40 | |
| - | - | |
| 9.0 | 6.2 | |
| 3 months ago | 9 days ago | |
| C | Verilog | |
| GNU General Public License v3.0 only | BSD 3-clause "New" or "Revised" License |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
eth10g
Posts with mentions or reviews of eth10g.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-06-10.
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Virtual FPGA
Since writing that article, I've learned how to use other simulators as well. Right now, for example, I'm working on a project that will require GTX transceivers. Without building an all Verilog (or I suppose VHDL) simulation, it'd be difficult to know (via simulation) if I have my interface to those transceivers right yet (or not). So I'm building an all Verilog simulation, to include Xilinx's simulation models of the GTX transceiver, to make sure I've got it done right. (Yes, this does include a simulated PLL to track the output of the GTX transceiver as it returns from the model of the FPGA and into my ethernet model ...)
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openXC7 - open source tools for Xilinx XC7 series
I am working on a 10G Ethernet switch project. One of the project's goals is to go from Verilog to bitstream using only open source tools. This includes the DDR3 controller. The project is still in early development, though, so ... we'll see how far it gets.
demo-projects
Posts with mentions or reviews of demo-projects.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2023-04-25.
What are some alternatives?
When comparing eth10g and demo-projects you can also consider the following projects:
Virtual-FPGA-Lab - This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.
serv - SERV - The SErial RISC-V CPU
nextpnr - nextpnr portable FPGA place and route tool
zipcpu - A small, light weight, RISC CPU soft core
corundum - Open source FPGA-based NIC and platform for in-network compute
darkriscv - opensouce RISC-V cpu core implemented in Verilog from scratch in one night!
hdl - HDL libraries and projects