eth10g
nextpnr
eth10g | nextpnr | |
---|---|---|
2 | 6 | |
135 | 1,234 | |
- | 2.7% | |
9.0 | 9.1 | |
4 months ago | 5 days ago | |
C | C++ | |
GNU General Public License v3.0 only | ISC License |
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
eth10g
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Virtual FPGA
Since writing that article, I've learned how to use other simulators as well. Right now, for example, I'm working on a project that will require GTX transceivers. Without building an all Verilog (or I suppose VHDL) simulation, it'd be difficult to know (via simulation) if I have my interface to those transceivers right yet (or not). So I'm building an all Verilog simulation, to include Xilinx's simulation models of the GTX transceiver, to make sure I've got it done right. (Yes, this does include a simulated PLL to track the output of the GTX transceiver as it returns from the model of the FPGA and into my ethernet model ...)
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openXC7 - open source tools for Xilinx XC7 series
I am working on a 10G Ethernet switch project. One of the project's goals is to go from Verilog to bitstream using only open source tools. This includes the DDR3 controller. The project is still in early development, though, so ... we'll see how far it gets.
nextpnr
- A Simulated Annealing FPGA Placer in Rust
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YoWASP aims to distribute up-to-date FOSS FPGA tools compiled to WebAssembly
If the name were an arbitrary word which didn't attempt to define itself, would that be any better? I don't see why the name must mean anything specific, nor why you should expect the name to explain what the project is. That's what the documentation or other descriptive text is for. That the name gives some understanding at first glance is a bonus.
PnR is "place and route", and is a very common acronym in the ASIC/FPGA/VLSI space. It seems fair to expect those who'd use this specialized variant of Yosys to also be familiar with PnR. For reference, here's [1] Yosys's PnR tool, which expands the acronym in its README title.
Realistically, if you're using Yosys tools, you're going to need to have some familiarity with the underlying flows anyway; in my experience they're very powerful but also pretty DIY. That's not great, but it's the reality. That's just the nature of the space right now, given the alternative is a ~$1M single user license.
[1] https://github.com/YosysHQ/nextpnr
- openXC7 - open source tools for Xilinx XC7 series
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Is there a Free, open source FPGA programming software?
Check out Nextpnr. There's only a few lines it supports, but it is expanding. Smaller devices are especially well supported.
- Renesas enters FPGA market with the first ultra-low-power, low-cost family
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Sobel Edge Detection with Icestudio and ULX3S FPGA board
I'm not much aware if it's already considered fully supported but as answered on this issue, ECP5 is the best supported FPGA for the toolchain(but its talking about nextpnr specifically tho). But personally, I found no problem with it.
What are some alternatives?
Virtual-FPGA-Lab - This repository contains the codebase for Virtual FPGA Lab in Makerchip contributing as a participant in Google Summer of Code 2021, under FOSSi Foundation.
oss-cad-suite-build - Multi-platform nightly builds of open source digital design and verification tools
demo-projects - Demo projects for various Kintex FPGA boards
learn-fpga - Learning FPGA, yosys, nextpnr, and RISC-V
ULX3S_FPGA_Sobel_Edge_Detection_OV7670 - Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board
openfpga - Open FPGA tools
VerilogCreator - VerilogCreator is a QtCreator based IDE for Verilog 2005