oberon VS THM-Oberon

This project is still a great example of a complete computer design, starting from Niklaus Wirth's own RISC5 CPU (not a RISC-V) and very simple peripherals over the OS, runtime/garbage collector, compiler, GUI and simple example applications.

One problem of the original implementation is that it was based on an old Xilinx Spartan 3 development board. This is not only no longer available, but it is one of the few FPGA boards that used 32 bit wide fast (12 ns IIRC) asynchronous SRAM chips. Wirth's hardware design relies heavily on this.

Some years ago, there was a compatible board, the OberonStation. However, it seems this is no longer manufactures: https://pcper.com/2015/12/meet-the-oberonstation-kid-friendl...

However, some modified designs exist that implement a cache in FPGA block RAM and an SDRAM controller. These can be used one more recent FPGA boards:

- FleaFPGA "Ohm" board with a Lattice ECP5 FPGA and 32 MB RAM (https://fleasystems.com/fleaFPGA_Ohm.html) - https://github.com/Basman74/Oberon_SDRAM

- Radiona ulx3s, another ECP5 in an open source design (https://github.com/emard/oberon) - https://github.com/emard/oberon

- PapilioPro using a Xilinx Spartan 6 LX, another open source PCB design (https://papilio.cc/index.php?n=Papilio.PapilioPro) - https://opencores.org/projects/oberon_sdram

Shameless plug: my student Rikke's port of Project Oberon to RV32I (this is a real RISC-V), however, we still need to find some time to build an FPGA-based SoC. Currently, it runs in emulation: https://github.com/solbjorg/oberon-riscv

The problem with recreating the original Project Oberon system hardware on a current FPGA board is that Prof. Wirth's original design for the Xilinx Spartan 3 starter kit board (https://reference.digilentinc.com/spartan-3/spartan-3) relied on the fact that this board had 1 MB of fast, 32 bit wide, asynchronous SRAM, which is easy to handle. Thus, the CPU clocked at 25 MHz didn't require a cache and even had cycles to spare for the framebuffer accesses.

The OberonStation board replicated this design by using two 16-bit wide SRAMs. All other current boards using SRAM only have a single 16-bit wide SRAM, so all accesses to machine words such as the RISC5 instructions would take two cycles; often, the RAM is also too small, e.g. the BlackIce (https://mystorm.uk) has only 512 kB.

Most of the boards on the market today have SRAM or DDR RAM, which makes controlling the external memory much more complex and requires significant changes to the nice and simple Project Oberon hardware. There are ports using SDRAM, e.g. for the ulx3s (https://radiona.org/ulx3s/, https://github.com/emard/oberon) or FleaFPGA and Papilio Pro (https://opencores.org/projects/oberon_sdram).

On a really large FPGA, you could get by using on-chip block RAM only, but FPGAs with 1 MB of block RAM are still quite expensive...

This should be possible - Hellwig Geisse (forgot to mention his project, sorry - https://github.com/hgeisse/THM-Oberon) is working on an Oberon port to the Terasic DE2-115 FPGA port, which also an Altera FPGA like the MiSTer. The basis of the MiSTer is a Terasic DE10 Nano FPGA board, which has a more recent Cyclone V FPGA (the DE2-115 has a Cyclone II).

The MiST (MiSTer's predecessor, https://github.com/mist-devel) would also be a nice platform.

More Oberon resources and links can be found here if you are interested: