THM-Oberon
Oberon_SDRAM
| THM-Oberon | Oberon_SDRAM | |
|---|---|---|
| 1 | 1 | |
| 7 | 7 | |
| - | - | |
| 6.8 | 10.0 | |
| 4 months ago | about 6 years ago | |
| Modula-2 | ||
| GNU General Public License v3.0 or later | - |
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THM-Oberon
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Project Oberon
This should be possible - Hellwig Geisse (forgot to mention his project, sorry - https://github.com/hgeisse/THM-Oberon) is working on an Oberon port to the Terasic DE2-115 FPGA port, which also an Altera FPGA like the MiSTer. The basis of the MiSTer is a Terasic DE10 Nano FPGA board, which has a more recent Cyclone V FPGA (the DE2-115 has a Cyclone II).
The MiST (MiSTer's predecessor, https://github.com/mist-devel) would also be a nice platform.
More Oberon resources and links can be found here if you are interested:
Oberon_SDRAM
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Project Oberon
This project is still a great example of a complete computer design, starting from Niklaus Wirth's own RISC5 CPU (not a RISC-V) and very simple peripherals over the OS, runtime/garbage collector, compiler, GUI and simple example applications.
One problem of the original implementation is that it was based on an old Xilinx Spartan 3 development board. This is not only no longer available, but it is one of the few FPGA boards that used 32 bit wide fast (12 ns IIRC) asynchronous SRAM chips. Wirth's hardware design relies heavily on this.
Some years ago, there was a compatible board, the OberonStation. However, it seems this is no longer manufactures: https://pcper.com/2015/12/meet-the-oberonstation-kid-friendl...
However, some modified designs exist that implement a cache in FPGA block RAM and an SDRAM controller. These can be used one more recent FPGA boards:
- FleaFPGA "Ohm" board with a Lattice ECP5 FPGA and 32 MB RAM (https://fleasystems.com/fleaFPGA_Ohm.html) - https://github.com/Basman74/Oberon_SDRAM
- Radiona ulx3s, another ECP5 in an open source design (https://github.com/emard/oberon) - https://github.com/emard/oberon
- PapilioPro using a Xilinx Spartan 6 LX, another open source PCB design (https://papilio.cc/index.php?n=Papilio.PapilioPro) - https://opencores.org/projects/oberon_sdram
Shameless plug: my student Rikke's port of Project Oberon to RV32I (this is a real RISC-V), however, we still need to find some time to build an FPGA-based SoC. Currently, it runs in emulation: https://github.com/solbjorg/oberon-riscv
What are some alternatives?
A2OS - Unofficial mirror of the ETH A2 repository
oberon
oberon-riscv - Oberon RISC-V port, based on Samuel Falvo's RISC-V compiler and Peter de Wachter's Project Norebo. Part of an academic project to evaluate Project Oberon on RISC-V.
oberonc - An Oberon-07 compiler for the JVM
fynedesk - A full desktop environment for Linux/Unix using Fyne