dbus_ti_link_uart_verilog
Verilog dbus (TI transfer bus) implementation and bridge to UART. High-performance link with TI calculators such as TI-89. (by rvalles)
ghdl-yosys-plugin
VHDL synthesis (based on ghdl) (by ghdl)
dbus_ti_link_uart_verilog | ghdl-yosys-plugin | |
---|---|---|
1 | 6 | |
8 | 292 | |
- | 1.0% | |
0.0 | 4.0 | |
over 2 years ago | 7 months ago | |
Verilog | VHDL | |
MIT License | GNU General Public License v3.0 only |
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
dbus_ti_link_uart_verilog
Posts with mentions or reviews of dbus_ti_link_uart_verilog.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-27.
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Project IceStorm: open-source toolchain for Lattice iCE40 FPGAs
IceStorm is how I got into FPGAs.
I learned the ropes by making (from scratch, reinventing many wheels) an interface between TI calculator comms port and a standard serial port.
https://github.com/rvalles/dbus_ti_link_uart_verilog
ghdl-yosys-plugin
Posts with mentions or reviews of ghdl-yosys-plugin.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2021-09-27.
- VHDL to Layout - how?
- Project IceStorm: open-source toolchain for Lattice iCE40 FPGAs
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Convert VHDL to verilog
You could use yosys with the GHDL frontent: https://github.com/ghdl/ghdl-yosys-plugin
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Need Advice for learning digital design and ASIC and FPGA design flow
Yes, you can do formal Verification with the free tool known as SymbiYosys. In general, you will need a license to use SymbiYosys with VHDL. However, there is a free plugin that many have used with some amount of success to verify VHDL modules.
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Formal (Hardware) Verification
Have you looked into the GHDL Yosys plugin for use with the open source version of SymbiYosys?
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Ice40 with VHDL
While Yosys, and the open source flows following it, work primarily on Verilog, there is a VHDL plugin that you can use to get some VHDL support. I know the plugin is marked as experimental, but I am also aware that many folks have used it successfully. Your own mileage might vary.
What are some alternatives?
When comparing dbus_ti_link_uart_verilog and ghdl-yosys-plugin you can also consider the following projects:
icestorm - Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentation (Reverse Engineered)
wb2axip - Bus bridges and other odds and ends