cordic
A series of CORDIC related projects (by ZipCPU)
sin_lut
Simple, parameterized sine lookup table (by aspdigital)
The number of mentions indicates the total number of mentions that we've tracked plus the number of user suggested alternatives.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
Stars - the number of stars that a project has on GitHub. Growth - month over month growth in stars.
Activity is a relative number indicating how actively a project is being developed. Recent commits have higher weight than older ones.
For example, an activity of 9.0 indicates that a project is amongst the top 10% of the most actively developed projects that we are tracking.
cordic
Posts with mentions or reviews of cordic.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-05-24.
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sin/cos LUT generate in Matlab for VHDL/FGPA
(Note: My own sinewave lookup table generator does not currently apply this half interval offset. I'll need to fix that.)
sin_lut
Posts with mentions or reviews of sin_lut.
We have used some of these posts to build our list of alternatives
and similar projects. The last one was on 2022-05-24.
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sin/cos LUT generate in Matlab for VHDL/FGPA
I came up with this, and it seems to work well enough.
What are some alternatives?
When comparing cordic and sin_lut you can also consider the following projects:
interpolation - Digital Interpolation Techniques Applied to Digital Signal Processing
dspfilters - A collection of demonstration digital filters
red-pitaya-notes - Notes on the Red Pitaya Open Source Instrument
Beagle_SDR_GPS - KiwiSDR: BeagleBone web-accessible shortwave receiver and software-defined GPS
karuta - Karuta HLS Compiler: High level synthesis from prototype based object oriented script language to RTL (Verilog) aiming to be useful for FPGA development.