conversion VS sv2v

Compare conversion vs sv2v and see what are their differences.

conversion

Universal converter between values of different types (by nikita-volkov)

sv2v

SystemVerilog to Verilog conversion (by zachjs)
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conversion sv2v
- 3
7 557
- -
0.0 7.6
over 8 years ago 14 days ago
Haskell Haskell
MIT License BSD 3-clause "New" or "Revised" License
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conversion

Posts with mentions or reviews of conversion. We have used some of these posts to build our list of alternatives and similar projects.

We haven't tracked posts mentioning conversion yet.
Tracking mentions began in Dec 2020.

sv2v

Posts with mentions or reviews of sv2v. We have used some of these posts to build our list of alternatives and similar projects.
  • Verilog functions and wires
    1 project | /r/Verilog | 11 Jun 2023
    I see what you mean by some online examples adding begin...end in functions. They are not actually required, and many people choose to leave it out (sv2v, lowRISC, BSG). I don't believe there is a benefit to adding them, and it just creates more opportunities for bugs that compilers/linters cannot check.
  • HDL desugaring
    1 project | /r/FPGA | 12 Aug 2022
    For verilog, I know SV2V exists: https://github.com/zachjs/sv2v
  • Unrolling Verilog generate statements
    1 project | /r/FPGA | 17 Dec 2021
    Maybe this would help? https://github.com/zachjs/sv2v

What are some alternatives?

When comparing conversion and sv2v you can also consider the following projects:

string-fromto - Conversions between common string types, as well as Base16/Base32/Base64

openlane - OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.

transient - A full stack, reactive architecture for general purpose programming. Algebraic and monadically composable primitives for concurrency, parallelism, event handling, transactions, multithreading, Web, and distributed computing with complete de-inversion of control (No callbacks, no blocking, pure state)

verilog_template - A template for starting a Verilog project with FuseSoC integration, Icarus simulation, Verilator linting, Yosys usage report, and VS Code syntax highlighting.

algebraic-classes - Conversions between algebraic classes and F-algebras.

rio-orphans - A standard library for Haskell

aeson-yaml - Encode any Aeson (JSON) value as YAML (in pure Haskell)

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