Sentinel-65X
corundum
Sentinel-65X | corundum | |
---|---|---|
1 | 28 | |
9 | 1,484 | |
- | 3.1% | |
7.4 | 9.0 | |
about 2 months ago | 14 days ago | |
C | Verilog | |
CERN Open Hardware Licence Version 2 - Permissive | GNU General Public License v3.0 or later |
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Sentinel-65X
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FuryGpu – Custom PCIe FPGA GPU
You might find the Sentinel 65X interesting in that the guy behind it basically said "the X16 is big and clunky and expensive, let's cut out that stuff".
https://github.com/studio8502/Sentinel-65X
It's not yet a deliverable product but watching the developers work on it has been an entertaining part of my doomscrolling diet.
corundum
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FuryGpu – Custom PCIe FPGA GPU
The GPU uses this: https://github.com/alexforencich/verilog-pcie . And there is an open-source 100G NIC here, including open source 10G/25G MACs: https://github.com/corundum/corundum
- Open sourceCorundum – FPGA-based NIC and platform for in-network compute
- TCP checksum computation
- Are there any free/open source Lattice ECP5 Ethernet MAC IP Cores?
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xilinx versal gty testbench/data gen?
Well, I did build this: https://github.com/corundum/corundum
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FPGA for finance industry
I would look into 10GbE PCS/MAC packet processors implemented under AXI Stream interfaces for example. There are open source examples https://github.com/corundum/corundum and https://netfpga.org/ .
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Computer Networking Nerd and EE Student Looking to build a Baremetal Network Driver on top of baremetal kernel? Is this possible and if so, I'd like some guidance!
I built my own 100 Gbps capable NIC, along with driver: https://github.com/corundum/corundum. You're welcome to ask if you have any questions, though it is quite a different animal from a 100 Mbps NIC you might have on a microcontroller.
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Device Drivers for Transceiver Questions (Specifically, PCIe)
If you're looking for resources, here's one rather comprehensive example of a high-performance FPGA design with a fully custom DMA engine and driver, that runs on both Xilinx and Intel FPGAs: https://github.com/corundum/corundum
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shift/concatenate in v/sv
I have no idea, but you're welcome to build the design and look at it yourself: https://github.com/corundum/corundum/tree/master/fpga/mqnic/NetFPGA_SUME/fpga. The barrel shifters are in the DMA engine, both the read DMA and write DMA engines have wide barrel shifters.
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Open source projects?
Dive right into the slack channel and introduce yourself. There is also a new contributor guide. /u/alexforencich/ is on these reddits and he may be able to chime in and give you more concrete suggestions.
What are some alternatives?
verilog-ethernet - Verilog Ethernet components for FPGA implementation
rssguard - Feed reader (and podcast player) which supports RSS/ATOM/JSON and many web-based feed services.
NvChad - Blazing fast Neovim config providing solid defaults and a beautiful UI, enhancing your neovim experience.
litex - Build your hardware, easily!
soft_riscv - Soft-core RISCV processor for RISCV 2018 competition
psram-tang-nano-9k - An open source PSRAM/HyperRAM controller for Sipeed Tang Nano 9K / Gowin GW1NR-LV9QN88PC6/15 FPGA
BYU_PYNQ_PR_Video_Pipeline - The Demo that was presented at FCCM.
hls4ml - Machine learning on FPGAs using HLS
SBusFPGA - Stuff to put a FPGA in a SBus system (SPARCstation)
hkd - Display-Server-Agnostic Hotkey Daemon for Linux
cocotbext-pcie - PCI express simulation framework for Cocotb
xfcp - Extensible FPGA control platform